| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | radeon/llvm: Use a custom inserter to lower CLAMP | Tom Stellard | 2012-05-25 | 1 | -10/+1 |
| * | radeon/llvm: Use a custom inserter to lower FABS | Tom Stellard | 2012-05-25 | 1 | -1/+1 |
| * | radeon/llvm: add FLT_TO_UINT, UINT_TO_FLT instructions | Vadim Girlin | 2012-05-25 | 1 | -0/+20 |
| * | radeon/llvm: prepare to revert the round mode state to default | Vadim Girlin | 2012-05-25 | 1 | -2/+9 |
| * | radeon/llvm: fix opcode for RECIP_UINT_r600 | Vadim Girlin | 2012-05-25 | 1 | -1/+1 |
| * | radeon/llvm: Lower UDIV using the Selection DAG | Tom Stellard | 2012-05-24 | 1 | -3/+3 |
| * | radeon/llvm: Remove auto-generated AMDIL->ISA conversion code | Tom Stellard | 2012-05-24 | 1 | -44/+6 |
| * | radeon/llvm: Remove AMDIL instructions MULHI, SMUL | Tom Stellard | 2012-05-24 | 1 | -6/+4 |
| * | radeon/llvm: Remove AMDIL bitshift instructions (SHL, SHR, USHR) | Tom Stellard | 2012-05-24 | 1 | -9/+6 |
| * | radeon/llvm: Remove AMDIL FTOI and ITOF instructions | Tom Stellard | 2012-05-24 | 1 | -6/+6 |
| * | radeon/llvm: Remove AMDIL EXP* instructions | Tom Stellard | 2012-05-24 | 1 | -3/+2 |
| * | radeon/llvm: Remove AMDIL ADD instructions | Tom Stellard | 2012-05-24 | 1 | -3/+2 |
| * | radeon/llvm: Remove AMDIL binary instrutions (OR, AND, XOR, NOT) | Tom Stellard | 2012-05-24 | 1 | -10/+7 |
| * | radeon/llvm: Remove AMDIL ROUND_NEAREST instruction | Tom Stellard | 2012-05-24 | 1 | -3/+2 |
| * | radeon/llvm: Remove AMDIL ROUND_POSINF instruction | Tom Stellard | 2012-05-24 | 1 | -3/+2 |
| * | radeon/llvm: Add custom SDNode for FRACT | Tom Stellard | 2012-05-24 | 1 | -3/+2 |
| * | radeon/llvm: Use -1 as true value for SET* integer instructions | Tom Stellard | 2012-05-24 | 1 | -10/+10 |
| * | radeon/llvm: Handle selectcc DAG node | Tom Stellard | 2012-05-20 | 1 | -26/+156 |
| * | radeon/llvm: Add DAG nodes for MIN instructions | Tom Stellard | 2012-05-17 | 1 | -7/+7 |
| * | radeon/llvm: Lower lrp intrinsic during ISel | Tom Stellard | 2012-05-17 | 1 | -7/+0 |
| * | radeon/llvm: Remove AMDIL MAD instruction defs | Tom Stellard | 2012-05-17 | 1 | -3/+3 |
| * | radeon/llvm: Remove AMDIL MUL_IEEE* instructions | Tom Stellard | 2012-05-17 | 1 | -3/+2 |
| * | radeon/llvm: Remove AMDIL floating-point ADD instruction defs | Tom Stellard | 2012-05-17 | 1 | -3/+3 |
| * | radeon/llvm: Remove AMDIL CMOVLOG* instruction defs | Tom Stellard | 2012-05-17 | 1 | -4/+5 |
| * | radeon/llvm: Remove sub patterns from AMDILInstrPatterns.td | Tom Stellard | 2012-05-17 | 1 | -1/+1 |
| * | radeon/llvm: Add custom SDNodes for MAX | Tom Stellard | 2012-05-17 | 1 | -5/+4 |
| * | radeon/llvm: add support for texture offsets, fix TEX_LD | Vadim Girlin | 2012-05-15 | 1 | -2/+5 |
| * | radeon/llvm: add SET_GRADIENTS*, fix SAMPLE_G | Vadim Girlin | 2012-05-15 | 1 | -2/+26 |
| * | radeon/llvm: use correct intrinsic for CEIL | Vadim Girlin | 2012-05-15 | 1 | -2/+2 |
| * | radeon/llvm: Fix Evergreen/Cayman tablegen predicates | Tom Stellard | 2012-05-11 | 1 | -1/+3 |
| * | radeon/llvm: Add some comments | Tom Stellard | 2012-05-10 | 1 | -2/+2 |
| * | radeon/llvm: Auto-encode RAT_WRITE_CACHELESS_eg | Tom Stellard | 2012-05-10 | 1 | -12/+0 |
| * | radeon/llvm: Don't rely on tablegen for lowering int_AMDGPU_load_const | Tom Stellard | 2012-05-09 | 1 | -3/+7 |
| * | radeon/llvm: Remove the EXPORT_REG instruction | Tom Stellard | 2012-05-08 | 1 | -3/+3 |
| * | radeon/llvm: Use a custom inserter to lower RESERVE_REG | Tom Stellard | 2012-05-08 | 1 | -0/+7 |
| * | radeon/llvm: Use a custom inserter to lower STORE_OUTPUT | Tom Stellard | 2012-05-08 | 1 | -0/+7 |
| * | radeon/llvm: Use a custom inserter to lower LOAD_INPUT | Tom Stellard | 2012-05-08 | 1 | -8/+7 |
| * | radeon/llvm: add support for CUBE ALU instruction | Vadim Girlin | 2012-05-08 | 1 | -1/+12 |
| * | radeon/llvm: add support for some ALU instructions | Vadim Girlin | 2012-05-08 | 1 | -10/+51 |
| * | radeon/llvm: add support for AHSR/LSHR/LSHL instructions | Vadim Girlin | 2012-05-08 | 1 | -0/+8 |
| * | radeon/llvm: add support for TXQ/TXF/DDX/DDY instructions | Vadim Girlin | 2012-05-08 | 1 | -0/+21 |
| * | radeon/llvm: add support for v4i32 | Vadim Girlin | 2012-05-08 | 1 | -0/+10 |
| * | r600g/llvm: Add pattern for llvm.AMDGPU.kill v2 | Dragomir Ivanov | 2012-04-30 | 1 | -0/+5 |
| * | r600g/llvm: Let ISel handle lowering to {INSERT,EXTRACT}_SUBREG | Tom Stellard | 2012-04-23 | 1 | -7/+10 |
| * | r600/llvm: Add LOAD_VTX instruction | Tom Stellard | 2012-04-23 | 1 | -0/+13 |
| * | radeonsi: initial WIP SI code | Tom Stellard | 2012-04-13 | 1 | -0/+931 |
