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path: root/src/gallium/drivers/radeon/R600Instructions.td
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* radeon/llvm: Fix lowering of vbuildTom Stellard2012-09-131-10/+10
* radeon/llvm: Fix isEG tablegen predicateTom Stellard2012-08-311-3/+5
* radeon/llvm: Cleanup R600Instructions.tdTom Stellard2012-08-241-92/+28
* radeon/llvm: Set End of Program bit on RAT instructionsTom Stellard2012-08-231-7/+11
* radeon/llvm: Lower RETFLAG DAG Node to S_ENDPGM on SITom Stellard2012-08-231-0/+8
* radeon/llvm: Mark JUMP as a pseudo instructionTom Stellard2012-08-231-1/+1
* radeon/llvm: Add flag operand to some instructionsTom Stellard2012-08-231-17/+39
* radeon/llvm: ExpandSpecialInstrs - Add support for cube instructionsTom Stellard2012-08-211-10/+21
* radeon/llvm: Lower implicit parameters before ISelTom Stellard2012-08-161-18/+0
* radeon/llvm: Add a predicated JUMP instructionVincent Lejeune2012-08-151-0/+9
* radeon/llvm: Support for predicate bitVincent Lejeune2012-08-151-5/+24
* radeon/llvm: Add live-in registers during DAG loweringTom Stellard2012-08-151-15/+0
* radeon/llvm: Lower store_output intrinsic during DAG loweringTom Stellard2012-08-151-7/+0
* radeon/llvm: Force VTX_READ instructions to use same reg for src and dstTom Stellard2012-08-151-0/+14
* radeon/llvm: Remove CMOVLOG DAG nodeTom Stellard2012-08-021-2/+2
* radeon/llvm: Rename all AMDIL* classes to AMDGPU*Tom Stellard2012-07-301-7/+7
* radeon/llvm: Move conditional pattern leafs to common tablegen fileTom Stellard2012-07-271-41/+0
* radeon/llvm: Use multiclasses for floating point loadsTom Stellard2012-07-111-10/+32
* radeon/llvm: Rename namespace from AMDIL to AMDGPUTom Stellard2012-07-091-2/+2
* radeon/llvm: Enable vec4 loads on R600Tom Stellard2012-06-291-0/+16
* radeon/llvm: Enable floating point stores on R600Tom Stellard2012-06-291-0/+6
* radeon/llvm: Emit raw ISA for vertex fetch instructionsTom Stellard2012-06-291-8/+94
* radeon/llvm: Turn on the BitExtract peephole optimizationTom Stellard2012-06-211-0/+21
* radeon/llvm: Lower ROTL to BIT_ALIGNTom Stellard2012-06-211-0/+7
* radeon/llvm: Fix sin/cos codegen on R700Török Edwin2012-06-191-19/+24
* radeon/llvm: Emulate RECIP_UINT instruction on CaymanTom Stellard2012-06-061-4/+11
* radeon/llvm: Fix MULLO* instructions on CaymanTom Stellard2012-06-061-7/+30
* r600g: Compute support for CaymanTom Stellard2012-06-061-48/+44
* radeon/llvm: Remove AMDIL VCREATE* instructionsTom Stellard2012-06-061-0/+3
* radeon/llvm: Remove AMDIL LOADCONST* instructionsTom Stellard2012-06-061-1/+20
* radeon/llvm: Fix VTX_READ patternsTom Stellard2012-06-011-3/+3
* radeon/llvm: Remove AMDIL GLOBALSTORE* instructionsTom Stellard2012-06-011-8/+13
* radeon/llvm: Remove AMDIL GLOBALLOAD* instructionsTom Stellard2012-06-011-95/+17
* radeon/llvm: Use a custom inserter for MASK_WRITETom Stellard2012-05-251-10/+22
* radeon/llvm: Use tablegen pattern to lower bitconvertTom Stellard2012-05-251-0/+5
* radeon/llvm: Use a custom inserter to lower FNEGTom Stellard2012-05-251-0/+1
* radeon/llvm: Use a custom inserter to lower CLAMPTom Stellard2012-05-251-10/+1
* radeon/llvm: Use a custom inserter to lower FABSTom Stellard2012-05-251-1/+1
* radeon/llvm: add FLT_TO_UINT, UINT_TO_FLT instructionsVadim Girlin2012-05-251-0/+20
* radeon/llvm: prepare to revert the round mode state to defaultVadim Girlin2012-05-251-2/+9
* radeon/llvm: fix opcode for RECIP_UINT_r600Vadim Girlin2012-05-251-1/+1
* radeon/llvm: Lower UDIV using the Selection DAGTom Stellard2012-05-241-3/+3
* radeon/llvm: Remove auto-generated AMDIL->ISA conversion codeTom Stellard2012-05-241-44/+6
* radeon/llvm: Remove AMDIL instructions MULHI, SMULTom Stellard2012-05-241-6/+4
* radeon/llvm: Remove AMDIL bitshift instructions (SHL, SHR, USHR)Tom Stellard2012-05-241-9/+6
* radeon/llvm: Remove AMDIL FTOI and ITOF instructionsTom Stellard2012-05-241-6/+6
* radeon/llvm: Remove AMDIL EXP* instructionsTom Stellard2012-05-241-3/+2
* radeon/llvm: Remove AMDIL ADD instructionsTom Stellard2012-05-241-3/+2
* radeon/llvm: Remove AMDIL binary instrutions (OR, AND, XOR, NOT)Tom Stellard2012-05-241-10/+7
* radeon/llvm: Remove AMDIL ROUND_NEAREST instructionTom Stellard2012-05-241-3/+2
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