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path: root/src/gallium/drivers/radeon/R600Instructions.td
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* radeon/llvm: Lower UDIV using the Selection DAGTom Stellard2012-05-241-3/+3
* radeon/llvm: Remove auto-generated AMDIL->ISA conversion codeTom Stellard2012-05-241-44/+6
* radeon/llvm: Remove AMDIL instructions MULHI, SMULTom Stellard2012-05-241-6/+4
* radeon/llvm: Remove AMDIL bitshift instructions (SHL, SHR, USHR)Tom Stellard2012-05-241-9/+6
* radeon/llvm: Remove AMDIL FTOI and ITOF instructionsTom Stellard2012-05-241-6/+6
* radeon/llvm: Remove AMDIL EXP* instructionsTom Stellard2012-05-241-3/+2
* radeon/llvm: Remove AMDIL ADD instructionsTom Stellard2012-05-241-3/+2
* radeon/llvm: Remove AMDIL binary instrutions (OR, AND, XOR, NOT)Tom Stellard2012-05-241-10/+7
* radeon/llvm: Remove AMDIL ROUND_NEAREST instructionTom Stellard2012-05-241-3/+2
* radeon/llvm: Remove AMDIL ROUND_POSINF instructionTom Stellard2012-05-241-3/+2
* radeon/llvm: Add custom SDNode for FRACTTom Stellard2012-05-241-3/+2
* radeon/llvm: Use -1 as true value for SET* integer instructionsTom Stellard2012-05-241-10/+10
* radeon/llvm: Handle selectcc DAG nodeTom Stellard2012-05-201-26/+156
* radeon/llvm: Add DAG nodes for MIN instructionsTom Stellard2012-05-171-7/+7
* radeon/llvm: Lower lrp intrinsic during ISelTom Stellard2012-05-171-7/+0
* radeon/llvm: Remove AMDIL MAD instruction defsTom Stellard2012-05-171-3/+3
* radeon/llvm: Remove AMDIL MUL_IEEE* instructionsTom Stellard2012-05-171-3/+2
* radeon/llvm: Remove AMDIL floating-point ADD instruction defsTom Stellard2012-05-171-3/+3
* radeon/llvm: Remove AMDIL CMOVLOG* instruction defsTom Stellard2012-05-171-4/+5
* radeon/llvm: Remove sub patterns from AMDILInstrPatterns.tdTom Stellard2012-05-171-1/+1
* radeon/llvm: Add custom SDNodes for MAXTom Stellard2012-05-171-5/+4
* radeon/llvm: add support for texture offsets, fix TEX_LDVadim Girlin2012-05-151-2/+5
* radeon/llvm: add SET_GRADIENTS*, fix SAMPLE_GVadim Girlin2012-05-151-2/+26
* radeon/llvm: use correct intrinsic for CEILVadim Girlin2012-05-151-2/+2
* radeon/llvm: Fix Evergreen/Cayman tablegen predicatesTom Stellard2012-05-111-1/+3
* radeon/llvm: Add some commentsTom Stellard2012-05-101-2/+2
* radeon/llvm: Auto-encode RAT_WRITE_CACHELESS_egTom Stellard2012-05-101-12/+0
* radeon/llvm: Don't rely on tablegen for lowering int_AMDGPU_load_constTom Stellard2012-05-091-3/+7
* radeon/llvm: Remove the EXPORT_REG instructionTom Stellard2012-05-081-3/+3
* radeon/llvm: Use a custom inserter to lower RESERVE_REGTom Stellard2012-05-081-0/+7
* radeon/llvm: Use a custom inserter to lower STORE_OUTPUTTom Stellard2012-05-081-0/+7
* radeon/llvm: Use a custom inserter to lower LOAD_INPUTTom Stellard2012-05-081-8/+7
* radeon/llvm: add support for CUBE ALU instructionVadim Girlin2012-05-081-1/+12
* radeon/llvm: add support for some ALU instructionsVadim Girlin2012-05-081-10/+51
* radeon/llvm: add support for AHSR/LSHR/LSHL instructionsVadim Girlin2012-05-081-0/+8
* radeon/llvm: add support for TXQ/TXF/DDX/DDY instructionsVadim Girlin2012-05-081-0/+21
* radeon/llvm: add support for v4i32Vadim Girlin2012-05-081-0/+10
* r600g/llvm: Add pattern for llvm.AMDGPU.kill v2Dragomir Ivanov2012-04-301-0/+5
* r600g/llvm: Let ISel handle lowering to {INSERT,EXTRACT}_SUBREGTom Stellard2012-04-231-7/+10
* r600/llvm: Add LOAD_VTX instructionTom Stellard2012-04-231-0/+13
* radeonsi: initial WIP SI codeTom Stellard2012-04-131-0/+931
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