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path: root/src/gallium/drivers/radeon/R600InstrInfo.cpp
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* radeon/llvm: Cleanup R600Instructions.tdTom Stellard2012-08-241-1/+0
* radeon/llvm: Fix some coding style issuesTom Stellard2012-08-231-20/+20
* radeon/llvm: Use the MCCodeEmitter for R600Tom Stellard2012-08-231-59/+3
* radeon/llvm: Remove the last uses of MachineOperand flagsTom Stellard2012-08-231-8/+21
* radeon/llvm: Add flag operand to some instructionsTom Stellard2012-08-231-2/+28
* radeon/llvm: Encapsulate setting of MachineOperand flagsTom Stellard2012-08-231-0/+10
* radeon/llvm: ExpandSpecialInstrs - Add support for cube instructionsTom Stellard2012-08-211-2/+4
* radeon/llvm: Add helper function for getting sub reg indicesTom Stellard2012-08-211-6/+3
* radeon/llvm: Add callbacks needed by if-cvtVincent Lejeune2012-08-151-2/+114
* radeon/llvm: Lower branch/branch_cond into predicated jumpVincent Lejeune2012-08-151-0/+196
* radeon/llvm: Support for predicate bitVincent Lejeune2012-08-151-1/+29
* radeon/llvm: Cleanup AMDGPUUtil.cppApostolos Bartziokas2012-08-151-0/+78
* radeon/llvm: Merge AMDILSubtarget into AMDGPUSubtargetTom Stellard2012-07-301-2/+2
* radeon/llvm: Merge AMDILTargetLowering class into AMDGPUTargetLoweringTom Stellard2012-07-301-0/+1
* radeon/llvm: Rename namespace from AMDIL to AMDGPUTom Stellard2012-07-091-13/+14
* radeon/llvm: Use the VLIW Scheduler for R600->NITom Stellard2012-06-211-0/+11
* radeon/llvm: Fix MULLO* instructions on CaymanTom Stellard2012-06-061-0/+5
* radeon/llvm: Remove obselete hooks for the ConvertToISA passTom Stellard2012-06-061-40/+0
* radeon/llvm: Add isMov() to AMDILInstrInfoTom Stellard2012-06-061-0/+11
* radeon/llvm: Eliminate CFGStructurizer dependency on AMDIL instructionsTom Stellard2012-06-011-0/+16
* radeon/llvm: Lower UDIV using the Selection DAGTom Stellard2012-05-241-35/+0
* radeon/llvm: Remove auto-generated AMDIL->ISA conversion codeTom Stellard2012-05-241-1/+1
* radeon/llvm: Remove AMDIL bitshift instructions (SHL, SHR, USHR)Tom Stellard2012-05-241-4/+0
* radeon/llvm: Remove AMDIL ADD instructionsTom Stellard2012-05-241-2/+0
* radeon/llvm: Remove AMDIL binary instrutions (OR, AND, XOR, NOT)Tom Stellard2012-05-241-2/+0
* radeon/llvm: Handle SETGE_INT, SETGE_UINT, and SETGT_UINT opcodesTom Stellard2012-05-241-0/+6
* radeon/llvm: Handle selectcc DAG nodeTom Stellard2012-05-201-0/+4
* radeon/llvm: Add some commentsTom Stellard2012-05-101-2/+2
* radeon/llvm: add support for AHSR/LSHR/LSHL instructionsVadim Girlin2012-05-081-0/+12
* r600g/llvm: Handle copies between vector registersTom Stellard2012-04-231-2/+20
* r600g/llvm: Remove debugging hack from R600InstrInfo::copyPhysReg()Tom Stellard2012-04-231-4/+0
* radeonsi: initial WIP SI codeTom Stellard2012-04-131-0/+109
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