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path: root/src/gallium/drivers/radeon/R600ISelLowering.cpp
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* radeon/llvm: Remove backend code from MesaTom Stellard2013-01-041-740/+0
| | | | | | | | | | | | This code now lives in an external tree. For the next Mesa release fetch the code from the master branch of this LLVM repo: http://cgit.freedesktop.org/~tstellar/llvm/ For all subsequent Mesa releases, fetch the code from the official LLVM project: www.llvm.org
* radeon/llvm: improve select_cc lowering to generate CND* more oftenVincent Lejeune2012-09-271-35/+54
| | | | | | | | v2: - Simplify isZero() - Remove a unused function prototype - Clean whitespace trails Reviewed-by: Tom Stellard <[email protected]>
* radeon/llvm: support for interpolation intrinsicsVincent Lejeune2012-09-221-1/+87
| | | | Reviewed-by: Tom Stellard <[email protected]>
* radeon/llvm: Add support for v4f32 stores on R600Tom Stellard2012-09-211-1/+2
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* radeon/llvm: Expand vector fadd and fmul on R600Tom Stellard2012-09-211-0/+3
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* radeon/llvm: Add optimization for FP_ROUNDTom Stellard2012-09-211-0/+26
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* radeon/llvm: Fix unused variable warningTom Stellard2012-09-171-1/+0
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* radeon/llvm: Move kernel arg lowering into R600TargetLowering classTom Stellard2012-09-171-0/+28
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* radeon/llvm: Add SHADER_TYPE instructionTom Stellard2012-09-111-0/+1
| | | | | | | This allows the program to specify the type of shader being compiled (e.g. PXEL, VERTEX, etc.) Reviewed-by: Michel Dänzer <[email protected]>
* radeon/llvm: do not convert f32 operand of select_cc nodeVincent Lejeune2012-09-041-20/+20
| | | | | | v2:-use camel coding style Reviewed-by: Tom Stellard <[email protected]>
* radeon/llvm: custom lowering for FP_TO_UINT when dst is i1 (bool)Vincent Lejeune2012-09-041-0/+22
| | | | | | v2:-wrap line at 80 characters Reviewed-by: Tom Stellard <[email protected]>
* radeon/llvm: support setcc on f32Vincent Lejeune2012-09-041-9/+27
| | | | Reviewed-by: Tom Stellard <[email protected]>
* radon/llvm: br_cc f32 now lowered without castVincent Lejeune2012-09-041-9/+24
| | | | Reviewed-by: Tom Stellard <[email protected]>
* radeon/llvm: swap wrong OPCODE_IS_*_ZERO_* opcode and useVincent Lejeune2012-09-041-2/+2
| | | | Reviewed-by: Tom Stellard <[email protected]>
* radeon/llvm: Set End of Program bit on RAT instructionsTom Stellard2012-08-231-1/+3
| | | | This code was accidently dropped during the MCCodeEmitter conversion.
* radeon/llvm: Use correct instruction for moving immediatesTom Stellard2012-08-231-1/+2
| | | | | This should fix an assertion failure that was happening in some compute shaders.
* radeon/llvm: Fix some coding style issuesTom Stellard2012-08-231-6/+6
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* radeon/llvm: Pull changes from external version of the backendTom Stellard2012-08-231-4/+4
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* radeon/llvm: Use the MCCodeEmitter for R600Tom Stellard2012-08-231-0/+1
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* radeon/llvm: Add flag operand to some instructionsTom Stellard2012-08-231-2/+7
| | | | | | | This new operand replaces the MachineOperand flags in LLVM, which will be deprecated soon. Eventually all instructions should have a flag operand, but for now this operand has only been added to instructions that need it.
* radeon/llvm: Encapsulate setting of MachineOperand flagsTom Stellard2012-08-231-42/+51
| | | | | MachineOperand flags will be removed soon, so it is convienent to have only one function that modifies them.
* radeon/llvm: Lower implicit parameters before ISelTom Stellard2012-08-161-49/+37
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* radeon/llvm: Lower branch/branch_cond into predicated jumpVincent Lejeune2012-08-151-0/+27
| | | | Signed-off-by: Tom Stellard <[email protected]>
* radeon/llvm: Support for predicate bitVincent Lejeune2012-08-151-4/+9
| | | | | | | Tom Stellard: - A few changes to predicate register defs Signed-off-by: Tom Stellard <[email protected]>
* radeon/llvm: Remove AMDGPUUtil.cppTom Stellard2012-08-151-1/+0
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* radeon/llvm: Add live-in registers during DAG loweringTom Stellard2012-08-151-27/+40
| | | | | | Psuedo instructions emulating live-in registers have been removed and their corresponding intrinsics are now being lowered during DAG lowering.
* radeon/llvm: Lower store_output intrinsic during DAG loweringTom Stellard2012-08-151-14/+21
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* radeon/llvm: Inline immediate offset when lowering implicit parametersTom Stellard2012-08-141-4/+8
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* radeon/llvm: Remove CMOVLOG DAG nodeTom Stellard2012-08-021-0/+6
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* radeon/llvm: Merge AMDILTargetLowering class into AMDGPUTargetLoweringTom Stellard2012-07-301-1/+3
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* radeon/llvm: Move lowering of BR_CC node to R600ISelLoweringTom Stellard2012-07-271-0/+29
| | | | | SI will handle BR_CC different from R600, so we need to move it out of the shared instruction selector.
* radeon/llvm: Move lowering of SETCC node to R600ISelLoweringTom Stellard2012-07-271-0/+28
| | | | | SI will handle SETCC different from R600, so we need to move it out of the shared instruction selector.
* radeon/llvm: Move LowerSELECT_CC into R600ISelLoweringTom Stellard2012-07-271-0/+110
| | | | | SI will handle SELECT_CC different from R600, so we need to move it out of the shared instruction selector.
* radeon/llvm: Use multiclasses for floating point loadsTom Stellard2012-07-111-1/+1
| | | | | | | The original strategy for handling floating point loads, which was to lower (f32 load) to (f32 bitcast (i32 load)) wasn't really working. The main problem was that the DAG legalizer couldn't handle replacing a node with two results (load) with a node with only one result (bitcast).
* radeon/llvm: Rename namespace from AMDIL to AMDGPUTom Stellard2012-07-091-65/+65
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* radeon/llvm: Lower ROTL to BIT_ALIGNTom Stellard2012-06-211-0/+28
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* radeon/llvm: Use the VLIW Scheduler for R600->NITom Stellard2012-06-211-1/+1
| | | | | | | | | | | | | | | | | | | It's not optimal, but it's better than the register pressure scheduler that was previously being used. The VLIW scheduler currently ignores all the complicated instruction groups restrictions and just tries to fill the instruction groups with as many instructions as possible. Though, it does know enough not to put two trans only instructions in the same group. We are able to ignore the instruction group restrictions in the LLVM backend, because the finalizer in r600_asm.c will fix any illegal instruction groups the backend generates. Enabling the VLIW scheduler improved the run time for a sha1 compute shader by about 50%. I'm not sure what the impact will be for graphics shaders. I tested Lightsmark with the VLIW scheduler enabled and the framerate was about the same, but it might help apps that use really big shaders.
* radeon/llvm: Remove deadcode from AMDILISelLowering.cppTom Stellard2012-06-181-5/+0
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* radeon/llvm: Remove AMDIL GLOBALSTORE* instructionsTom Stellard2012-06-011-0/+23
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* radeon/llvm: Remove AMDIL GLOBALLOAD* instructionsTom Stellard2012-06-011-4/+4
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* radeon/llvm: Update and fix some commentsTom Stellard2012-05-291-7/+1
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* radeonsi: Handle TGSI CONST registersTom Stellard2012-05-291-0/+1
| | | | | We now emit LLVM load instructions for TGSI CONST register reads, which are lowered in the backend to S_LOAD_DWORD* instructions.
* radeon/llvm: Use a custom inserter for MASK_WRITETom Stellard2012-05-251-0/+12
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* radeon/llvm: Use a custom inserter to lower FNEGTom Stellard2012-05-251-0/+7
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* radeon/llvm: Use a custom inserter to lower CLAMPTom Stellard2012-05-251-0/+7
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* radeon/llvm: Use a custom inserter to lower FABSTom Stellard2012-05-251-0/+8
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* radeon/llvm: Handle selectcc DAG nodeTom Stellard2012-05-201-0/+7
| | | | | R600 can now select instructions from the selectcc DAG node, which is typically lowered to one of the SET* instructions.
* radeon/llvm: Expand fsub during ISelTom Stellard2012-05-171-0/+2
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* radeon/llvm: add SET_GRADIENTS*, fix SAMPLE_GVadim Girlin2012-05-151-0/+47
| | | | | Signed-off-by: Vadim Girlin <[email protected]> Reviewed-by: Tom Stellard <[email protected]>
* radeon/llvm: Add some commentsTom Stellard2012-05-101-3/+3
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