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path: root/src/gallium/drivers/radeon/R600ISelLowering.cpp
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* radeon/llvm: Set End of Program bit on RAT instructionsTom Stellard2012-08-231-1/+3
* radeon/llvm: Use correct instruction for moving immediatesTom Stellard2012-08-231-1/+2
* radeon/llvm: Fix some coding style issuesTom Stellard2012-08-231-6/+6
* radeon/llvm: Pull changes from external version of the backendTom Stellard2012-08-231-4/+4
* radeon/llvm: Use the MCCodeEmitter for R600Tom Stellard2012-08-231-0/+1
* radeon/llvm: Add flag operand to some instructionsTom Stellard2012-08-231-2/+7
* radeon/llvm: Encapsulate setting of MachineOperand flagsTom Stellard2012-08-231-42/+51
* radeon/llvm: Lower implicit parameters before ISelTom Stellard2012-08-161-49/+37
* radeon/llvm: Lower branch/branch_cond into predicated jumpVincent Lejeune2012-08-151-0/+27
* radeon/llvm: Support for predicate bitVincent Lejeune2012-08-151-4/+9
* radeon/llvm: Remove AMDGPUUtil.cppTom Stellard2012-08-151-1/+0
* radeon/llvm: Add live-in registers during DAG loweringTom Stellard2012-08-151-27/+40
* radeon/llvm: Lower store_output intrinsic during DAG loweringTom Stellard2012-08-151-14/+21
* radeon/llvm: Inline immediate offset when lowering implicit parametersTom Stellard2012-08-141-4/+8
* radeon/llvm: Remove CMOVLOG DAG nodeTom Stellard2012-08-021-0/+6
* radeon/llvm: Merge AMDILTargetLowering class into AMDGPUTargetLoweringTom Stellard2012-07-301-1/+3
* radeon/llvm: Move lowering of BR_CC node to R600ISelLoweringTom Stellard2012-07-271-0/+29
* radeon/llvm: Move lowering of SETCC node to R600ISelLoweringTom Stellard2012-07-271-0/+28
* radeon/llvm: Move LowerSELECT_CC into R600ISelLoweringTom Stellard2012-07-271-0/+110
* radeon/llvm: Use multiclasses for floating point loadsTom Stellard2012-07-111-1/+1
* radeon/llvm: Rename namespace from AMDIL to AMDGPUTom Stellard2012-07-091-65/+65
* radeon/llvm: Lower ROTL to BIT_ALIGNTom Stellard2012-06-211-0/+28
* radeon/llvm: Use the VLIW Scheduler for R600->NITom Stellard2012-06-211-1/+1
* radeon/llvm: Remove deadcode from AMDILISelLowering.cppTom Stellard2012-06-181-5/+0
* radeon/llvm: Remove AMDIL GLOBALSTORE* instructionsTom Stellard2012-06-011-0/+23
* radeon/llvm: Remove AMDIL GLOBALLOAD* instructionsTom Stellard2012-06-011-4/+4
* radeon/llvm: Update and fix some commentsTom Stellard2012-05-291-7/+1
* radeonsi: Handle TGSI CONST registersTom Stellard2012-05-291-0/+1
* radeon/llvm: Use a custom inserter for MASK_WRITETom Stellard2012-05-251-0/+12
* radeon/llvm: Use a custom inserter to lower FNEGTom Stellard2012-05-251-0/+7
* radeon/llvm: Use a custom inserter to lower CLAMPTom Stellard2012-05-251-0/+7
* radeon/llvm: Use a custom inserter to lower FABSTom Stellard2012-05-251-0/+8
* radeon/llvm: Handle selectcc DAG nodeTom Stellard2012-05-201-0/+7
* radeon/llvm: Expand fsub during ISelTom Stellard2012-05-171-0/+2
* radeon/llvm: add SET_GRADIENTS*, fix SAMPLE_GVadim Girlin2012-05-151-0/+47
* radeon/llvm: Add some commentsTom Stellard2012-05-101-3/+3
* radeon/llvm: Delete all instructions that have been custom loweredTom Stellard2012-05-101-4/+1
* radeon/llvm: Don't rely on tablegen for lowering int_AMDGPU_load_constTom Stellard2012-05-091-1/+13
* radeon/llvm: Remove the EXPORT_REG instructionTom Stellard2012-05-081-3/+2
* radeon/llvm: Use a custom inserter to lower RESERVE_REGTom Stellard2012-05-081-0/+13
* radeon/llvm: Use a custom inserter to lower STORE_OUTPUTTom Stellard2012-05-081-0/+16
* radeon/llvm: Use a custom inserter to lower LOAD_INPUTTom Stellard2012-05-081-1/+8
* radeon/llvm: add support for v4i32Vadim Girlin2012-05-081-0/+4
* r600g/llvm: Let ISel handle lowering to {INSERT,EXTRACT}_SUBREGTom Stellard2012-04-231-0/+5
* radeonsi: initial WIP SI codeTom Stellard2012-04-131-0/+102
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