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* radeon/llvm: Fix instruction encoding for r600 family GPUsTom Stellard2012-09-241-2/+2
* radeon/llvm: Handle loads from the constants address space.Tom Stellard2012-09-211-0/+1
* radeon/llvm: Add support for v4f32 stores on R600Tom Stellard2012-09-211-1/+2
* radeon/llvm: Add support for i8 reads on R600Tom Stellard2012-09-211-0/+1
* radeon/llvm: Emit ISA for ALU instructions in the R600 code emitterMichal Sciubidlo2012-09-191-87/+122
* radeon/llvm: Add register encoding for VCCTom Stellard2012-09-111-0/+1
* radeon/llvm: Extend SI EXEC register support.Michel Dänzer2012-09-061-0/+3
* radeon/llvm: Rework how immediate operands are handled with SITom Stellard2012-08-311-25/+14
* radeon/llvm: Fix encoding of FP immediates on SITom Stellard2012-08-291-1/+6
* radeon/llvm: Set End of Program bit on RAT instructionsTom Stellard2012-08-231-2/+0
* radeon/llvm: Fix some coding style issuesTom Stellard2012-08-234-33/+22
* radeon/llvm: Pull changes from external version of the backendTom Stellard2012-08-237-22/+22
* radeon/llvm: Use the MCCodeEmitter for R600Tom Stellard2012-08-234-13/+724
* radeon/llvm: Use the MCCodeEmitter for SITom Stellard2012-08-236-6/+478
* radeon/llvm: Add AsmPrinterTom Stellard2012-08-231-0/+11
* radeon/llvm: Change the tablegen target from AMDIL to AMDGPUTom Stellard2012-07-301-11/+11
* radeon/llvm: Change prefix on tablegen files to AMDGPUTom Stellard2012-06-012-6/+6
* radeon/llvm: Remove AMDILTargetMachineTom Stellard2012-05-292-7/+1
* radeonsi: initial WIP SI codeTom Stellard2012-04-134-0/+239