| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | radeon/llvm: Fix instruction encoding for r600 family GPUs | Tom Stellard | 2012-09-24 | 1 | -2/+2 |
| * | radeon/llvm: Handle loads from the constants address space. | Tom Stellard | 2012-09-21 | 1 | -0/+1 |
| * | radeon/llvm: Add support for v4f32 stores on R600 | Tom Stellard | 2012-09-21 | 1 | -1/+2 |
| * | radeon/llvm: Add support for i8 reads on R600 | Tom Stellard | 2012-09-21 | 1 | -0/+1 |
| * | radeon/llvm: Emit ISA for ALU instructions in the R600 code emitter | Michal Sciubidlo | 2012-09-19 | 1 | -87/+122 |
| * | radeon/llvm: Set End of Program bit on RAT instructions | Tom Stellard | 2012-08-23 | 1 | -2/+0 |
| * | radeon/llvm: Fix some coding style issues | Tom Stellard | 2012-08-23 | 1 | -12/+0 |
| * | radeon/llvm: Pull changes from external version of the backend | Tom Stellard | 2012-08-23 | 1 | -1/+1 |
| * | radeon/llvm: Use the MCCodeEmitter for R600 | Tom Stellard | 2012-08-23 | 1 | -0/+703 |
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