| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | radeonsi: Handle TGSI TXQ opcode | Michel Dänzer | 2013-05-28 | 1 | -1/+1 |
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| * | radeonsi: Add support for TGSI TXF opcode | Michel Dänzer | 2013-05-28 | 1 | -1/+1 |
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| * | r600g/llvm: Parse config values in register / value pairs | Tom Stellard | 2013-05-06 | 1 | -1/+1 |
| | | | | | Rather than relying on a predetermined order for the config values. | ||||
| * | r600g/llvm: Don't feed LLVM output through r600_bytecode_build() | Tom Stellard | 2013-05-06 | 1 | -1/+1 |
| | | | | | | The LLVM backend emits raw ISA now, so we can just its output unmodified. | ||||
| * | r600g/llvm: Don't emit CALL_FS for vertex shaders | Tom Stellard | 2013-05-06 | 1 | -1/+1 |
| | | | | | The LLVM backend takes care of this now. | ||||
| * | r600g/llvm: Update radeon family mappings for LLVM backend | Tom Stellard | 2013-05-06 | 1 | -1/+1 |
| | | | | | | New processors were added to the backend to distinguish between GPUs with and without vertex caches. | ||||
| * | r600g/llvm: get use_kill from compiler shader | Vincent Lejeune | 2013-04-30 | 1 | -1/+1 |
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| * | r600/llvm: Read stacksize from config header | Vincent Lejeune | 2013-04-23 | 1 | -1/+1 |
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| * | /bin/bash: q : commande introuvable | Vincent Lejeune | 2013-04-23 | 1 | -1/+1 |
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| * | r600g/llvm: Use gprcount from llvm | Vincent Lejeune | 2013-04-17 | 1 | -1/+1 |
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| * | radeonsi: Read config values from the .AMDGPU.config ELF section | Tom Stellard | 2013-04-15 | 1 | -1/+1 |
| | | | | | | | | | | Instead of emitting configuration values (e.g. number of gprs used) in a predefined order, the LLVM backend now emits these values in register/value pairs. The first dword contains the register address and the second dword contians the value to write. Reviewed-by: Michel Dänzer <[email protected]> | ||||
| * | radeon/llvm: Handle ELF formatted binary output from the LLVM backend | Tom Stellard | 2013-04-15 | 1 | -1/+1 |
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| * | radeonsi: remove sampler writemask v3 | Christian König | 2013-04-10 | 1 | -1/+1 |
| | | | | | | | | | v2: fix instrinsic name as well v3: LLVM revision incremented as well Signed-off-by: Christian König <[email protected]> Reviewed-by: Michel Dänzer <[email protected]> | ||||
| * | r600g/llvm: Add support for native isa for pre EG | Vincent Lejeune | 2013-04-08 | 1 | -1/+1 |
| | | | | | | This fixes bug 62756 : https://bugs.freedesktop.org/show_bug.cgi?id=62756#c12 | ||||
| * | gallium: PIPE_COMPUTE_CAP_IR_TARGET - allow drivers to specify a processor v2 | Tom Stellard | 2013-04-05 | 1 | -1/+1 |
| | | | | | | | | | | | | | This target string now contains four values instead of three. The old processor field (which was really being interpreted as arch) has been split into two fields: processor and arch. This allows drivers to pass a more a more detailed description of the hardware to compiler frontends. v2: - Adapt to libclc changes Reviewed-by: Francisco Jerez <[email protected]> | ||||
| * | r600g/llvm: Update LLVM_REVISION.txt | Vincent Lejeune | 2013-04-01 | 1 | -1/+1 |
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| * | r600g/llvm: Update LLVM_REVISION | Vincent Lejeune | 2013-03-31 | 1 | -1/+1 |
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| * | radeon/llvm: document LLVM commit | Christian König | 2013-03-26 | 1 | -1/+1 |
| | | | | | | | We need at least that revision to work correctly now. Signed-off-by: Christian König <[email protected]> | ||||
| * | radeon/llvm: document LLVM commit | Christian König | 2013-03-07 | 1 | -0/+1 |
| We need at least that revision to work correctly now. Signed-off-by: Christian König <[email protected]> | |||||
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