Commit message (Collapse) | Author | Age | Files | Lines | |
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* | radeon/llvm: Remove backend code from Mesa | Tom Stellard | 2013-01-04 | 1 | -66/+0 |
| | | | | | | | | | | | | This code now lives in an external tree. For the next Mesa release fetch the code from the master branch of this LLVM repo: http://cgit.freedesktop.org/~tstellar/llvm/ For all subsequent Mesa releases, fetch the code from the official LLVM project: www.llvm.org | ||||
* | radeon/llvm: Emit ISA for ALU instructions in the R600 code emitter | Michal Sciubidlo | 2012-09-19 | 1 | -0/+2 |
| | | | | Signed-off-by: Tom Stellard <[email protected]> | ||||
* | radeon/llvm: Rename all AMDIL* classes to AMDGPU* | Tom Stellard | 2012-07-30 | 1 | -4/+4 |
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* | radeon/llvm: Merge AMDILSubtarget into AMDGPUSubtarget | Tom Stellard | 2012-07-30 | 1 | -2/+30 |
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* | radeon/llvm: Change the tablegen target from AMDIL to AMDGPU | Tom Stellard | 2012-07-30 | 1 | -5/+5 |
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* | radeon/llvm: Use the VLIW Scheduler for R600->NI | Tom Stellard | 2012-06-21 | 1 | -0/+36 |
It's not optimal, but it's better than the register pressure scheduler that was previously being used. The VLIW scheduler currently ignores all the complicated instruction groups restrictions and just tries to fill the instruction groups with as many instructions as possible. Though, it does know enough not to put two trans only instructions in the same group. We are able to ignore the instruction group restrictions in the LLVM backend, because the finalizer in r600_asm.c will fix any illegal instruction groups the backend generates. Enabling the VLIW scheduler improved the run time for a sha1 compute shader by about 50%. I'm not sure what the impact will be for graphics shaders. I tested Lightsmark with the VLIW scheduler enabled and the framerate was about the same, but it might help apps that use really big shaders. |