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path: root/src/gallium/drivers/radeon/AMDGPUInstructions.td
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* radeon/llvm: Add support for i8 reads on R600Tom Stellard2012-09-211-0/+8
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* radeon/llvm: Replace AMDGPU pow intrinsic with the llvm versionTom Stellard2012-09-211-1/+1
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* radeon/llvm: Fix lowering of vbuildTom Stellard2012-09-131-3/+7
| | | | | | Some of the old AMDIL code was hard-coding subreg indices when creating the VBUILD node, which was making it difficult to match the vector_insert patterns.
* radeon/llvm: Add SHADER_TYPE instructionTom Stellard2012-09-111-0/+7
| | | | | | | This allows the program to specify the type of shader being compiled (e.g. PXEL, VERTEX, etc.) Reviewed-by: Michel Dänzer <[email protected]>
* radeon/llvm: Move conditional pattern leafs to common tablegen fileTom Stellard2012-07-271-0/+41
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* radeon/llvm: Rename namespace from AMDIL to AMDGPUTom Stellard2012-07-091-1/+1
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* radeon/llvm: Use the VLIW Scheduler for R600->NITom Stellard2012-06-211-0/+1
| | | | | | | | | | | | | | | | | | | It's not optimal, but it's better than the register pressure scheduler that was previously being used. The VLIW scheduler currently ignores all the complicated instruction groups restrictions and just tries to fill the instruction groups with as many instructions as possible. Though, it does know enough not to put two trans only instructions in the same group. We are able to ignore the instruction group restrictions in the LLVM backend, because the finalizer in r600_asm.c will fix any illegal instruction groups the backend generates. Enabling the VLIW scheduler improved the run time for a sha1 compute shader by about 50%. I'm not sure what the impact will be for graphics shaders. I tested Lightsmark with the VLIW scheduler enabled and the framerate was about the same, but it might help apps that use really big shaders.
* radeon/llvm: Remove AMDIL VCREATE* instructionsTom Stellard2012-06-061-0/+6
| | | | This obsoletes the AMDGPULowerInstruction pass.
* radeon/llvm: Use a custom inserter for MASK_WRITETom Stellard2012-05-251-13/+2
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* radeon/llvm: Use tablegen pattern to lower bitconvertTom Stellard2012-05-251-0/+6
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* radeon/llvm: Use a custom inserter to lower FNEGTom Stellard2012-05-251-0/+7
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* radeon/llvm: Use a custom inserter to lower CLAMPTom Stellard2012-05-251-0/+17
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* radeon/llvm: Use a custom inserter to lower FABSTom Stellard2012-05-251-1/+13
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* radeon/llvm: Remove auto-generated AMDIL->ISA conversion codeTom Stellard2012-05-241-2/+7
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* radeon/llvm: Add some commentsTom Stellard2012-05-101-2/+3
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* radeon/llvm: Remove the EXPORT_REG instructionTom Stellard2012-05-081-7/+0
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* radeon/llvm: Use a custom inserter to lower RESERVE_REGTom Stellard2012-05-081-7/+0
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* radeon/llvm: Use a custom inserter to lower STORE_OUTPUTTom Stellard2012-05-081-7/+0
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* radeon/llvm: Use a custom inserter to lower LOAD_INPUTTom Stellard2012-05-081-6/+0
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* radeon/llvm: Remove the ReorderPreloadInstructions passTom Stellard2012-05-081-8/+3
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* r600g/llvm: Let ISel handle lowering to {INSERT,EXTRACT}_SUBREGTom Stellard2012-04-231-0/+21
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* radeonsi: initial WIP SI codeTom Stellard2012-04-131-0/+90
This commit adds initial support for acceleration on SI chips. egltri is starting to work. The SI/R600 llvm backend is currently included in mesa but that may change in the future. The plan is to write a single gallium driver and use gallium to support X acceleration. This commit contains patches from: Tom Stellard <[email protected]> Michel Dänzer <[email protected]> Alex Deucher <[email protected]> Vadim Girlin <[email protected]> Signed-off-by: Alex Deucher <[email protected]> The following commits were squashed in: ====================================================================== radeonsi: Remove unused winsys pointer This was removed from r600g in commit: commit 96d882939d612fcc8332f107befec470ed4359de Author: Marek Olšák <[email protected]> Date: Fri Feb 17 01:49:49 2012 +0100 gallium: remove unused winsys pointers in pipe_screen and pipe_context A winsys is already a private object of a driver. ====================================================================== radeonsi: Copy color clamping CAPs from r600 Not sure if the values of these CAPS are correct for radeonsi, but the same changed were made to r600g in commit: commit bc1c8369384b5e16547c5bf9728aa78f8dfd66cc Author: Marek Olšák <[email protected]> Date: Mon Jan 23 03:11:17 2012 +0100 st/mesa: do vertex and fragment color clamping in shaders For ARB_color_buffer_float. Most hardware can't do it and st/mesa is the perfect place for a fallback. The exceptions are: - r500 (vertex clamp only) - nv50 (both) - nvc0 (both) - softpipe (both) We also have to take into account that r300 can do CLAMPED vertex colors only, while r600 can do UNCLAMPED vertex colors only. The difference can be expressed with the two new CAPs. ====================================================================== radeonsi: Remove PIPE_CAP_OUTPUT_READ This CAP was dropped in commit: commit 04e324008759282728a95a1394bac2c4c2a1a3f9 Author: Marek Olšák <[email protected]> Date: Thu Feb 23 23:44:36 2012 +0100 gallium: remove PIPE_SHADER_CAP_OUTPUT_READ r600g is the only driver which has made use of it. The reason the CAP was added was to fix some piglit tests when the GLSL pass lower_output_reads didn't exist. However, not removing output reads breaks the fallback for glClampColorARB, which assumes outputs are not readable. The fix would be non-trivial and my personal preference is to remove the CAP, considering that reading outputs is uncommon and that we can now use lower_output_reads to fix the issue that the CAP was supposed to workaround in the first place. ====================================================================== radeonsi: Add missing parameters to rws->buffer_get_tiling() call This was changed in commit: commit c0c979eebc076b95cc8d18a013ce2968fe6311ad Author: Jerome Glisse <[email protected]> Date: Mon Jan 30 17:22:13 2012 -0500 r600g: add support for common surface allocator for tiling v13 Tiled surface have all kind of alignment constraint that needs to be met. Instead of having all this code duplicated btw ddx and mesa use common code in libdrm_radeon this also ensure that both ddx and mesa compute those alignment in the same way. v2 fix evergreen v3 fix compressed texture and workaround cube texture issue by disabling 2D array mode for cubemap (need to check if r7xx and newer are also affected by the issue) v4 fix texture array v5 fix evergreen and newer, split surface values computation from mipmap tree generation so that we can get them directly from the ddx v6 final fix to evergreen tile split value v7 fix mipmap offset to avoid to use random value, use color view depth view to address different layer as hardware is doing some magic rotation depending on the layer v8 fix COLOR_VIEW on r6xx for linear array mode, use COLOR_VIEW on evergreen, align bytes per pixel to a multiple of a dword v9 fix handling of stencil on evergreen, half fix for compressed texture v10 fix evergreen compressed texture proper support for stencil tile split. Fix stencil issue when array mode was clear by the kernel, always program stencil bo. On evergreen depth buffer bo need to be big enough to hold depth buffer + stencil buffer as even with stencil disabled things get written there. v11 rebase on top of mesa, fix pitch issue with 1d surface on evergreen, old ddx overestimate those. Fix linear case when pitch*height < 64. Fix r300g. v12 Fix linear case when pitch*height < 64 for old path, adapt to libdrm API change v13 add libdrm check Signed-off-by: Jerome Glisse <[email protected]> ====================================================================== radeonsi: Remove PIPE_TRANSFER_MAP_PERMANENTLY This was removed in commit: commit 62f44f670bb0162e89fd4786af877f8da9ff607c Author: Marek Olšák <[email protected]> Date: Mon Mar 5 13:45:00 2012 +0100 Revert "gallium: add flag PIPE_TRANSFER_MAP_PERMANENTLY" This reverts commit 0950086376b1c8b7fb89eda81ed7f2f06dee58bc. It was decided to refactor the transfer API instead of adding workarounds to address the performance issues. ====================================================================== radeonsi: Handle PIPE_VIDEO_CAP_PREFERED_FORMAT. Reintroduced in commit 9d9afcb5bac2931d4b8e6d1aa571e941c5110c90. ====================================================================== radeonsi: nuke the fallback for vertex and fragment color clamping Ported from r600g commit c2b800cf38b299c1ab1c53dc0e4ea00c7acef853. ====================================================================== radeonsi: don't expose transform_feedback2 without kernel support Ported from r600g commit 15146fd1bcbb08e44a1cbb984440ee1a5de63d48. ====================================================================== radeonsi: Handle PIPE_CAP_GLSL_FEATURE_LEVEL. Ported from r600g part of commit 171be755223d99f8cc5cc1bdaf8bd7b4caa04b4f. ====================================================================== radeonsi: set minimum point size to 1.0 for non-sprite non-aa points. Ported from r600g commit f183cc9ce3ad1d043bdf8b38fd519e8f437714fc. ====================================================================== radeonsi: rework and consolidate stencilref state setting. Ported from r600g commit a2361946e782b57f0c63587841ca41c0ea707070. ====================================================================== radeonsi: cleanup setting DB_SHADER_CONTROL. Ported from r600g commit 3d061caaed13b646ff40754f8ebe73f3d4983c5b. ====================================================================== radeonsi: Get rid of register masks. Ported from r600g commits 3d061caaed13b646ff40754f8ebe73f3d4983c5b..9344ab382a1765c1a7c2560e771485edf4954fe2. ====================================================================== radeonsi: get rid of r600_context_reg. Ported from r600g commits 9344ab382a1765c1a7c2560e771485edf4954fe2..bed20f02a771f43e1c5092254705701c228cfa7f. ====================================================================== radeonsi: Fix regression from 'Get rid of register masks'. ====================================================================== radeonsi: optimize r600_resource_va. Ported from r600g commit 669d8766ff3403938794eb80d7769347b6e52174. ====================================================================== radeonsi: remove u8,u16,u32,u64 types. Ported from r600g commit 78293b99b23268e6698f1267aaf40647c17d95a5. ====================================================================== radeonsi: merge r600_context with r600_pipe_context. Ported from r600g commit e4340c1908a6a3b09e1a15d5195f6da7d00494d0. ====================================================================== radeonsi: Miscellaneous context cleanups. Ported from r600g commits e4340c1908a6a3b09e1a15d5195f6da7d00494d0..621e0db71c5ddcb379171064a4f720c9cf01e888. ====================================================================== radeonsi: add a new simple API for state emission. Ported from r600g commits 621e0db71c5ddcb379171064a4f720c9cf01e888..f661405637bba32c2cfbeecf6e2e56e414e9521e. ====================================================================== radeonsi: Also remove sbu_flags member of struct r600_reg. Requires using sid.h instead of r600d.h for the new CP_COHER_CNTL definitions, so some code needs to be disabled for now. ====================================================================== radeonsi: Miscellaneous simplifications. Ported from r600g commits 38bf2763482b4f1b6d95cd51aecec75601d8b90f and b0337b679ad4c2feae59215104cfa60b58a619d5. ====================================================================== radeonsi: Handle PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION. Ported from commit 8b4f7b0672d663273310fffa9490ad996f5b914a. ====================================================================== radeonsi: Use a fake reloc to sleep for fences. Ported from r600g commit 8cd03b933cf868ff867e2db4a0937005a02fd0e4. ====================================================================== radeonsi: adapt to get_query_result interface change. Ported from r600g commit 4445e170bee23a3607ece0e010adef7058ac6a11.
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