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* gallium: add GREMEDY_string_markerRob Clark2016-01-211-0/+1
| | | | | | | | | | Since the GREMEDY extensions are normally only exposed by the gremedy debugger (and could possibly trigger debug paths in the app), we don't expose the extension by default, but instead only with ST_DEBUG=gremedy. Signed-off-by: Rob Clark <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* r600g: don't leak driver const buffersGrazvydas Ignotas2016-01-211-0/+6
| | | | | | | | | | | The buffers are referenced from r600_update_driver_const_buffers() -> r600_set_constant_buffer() -> u_upload_data(), but nothing ever releases the reference. Similar case with driver_consts. Found using valgrind. Signed-off-by: Grazvydas Ignotas <[email protected]> Cc: <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/st: add pipe_context::generate_mipmap()Charmaine Lee2016-01-141-0/+1
| | | | | | | | | | | | | | | | This patch adds a new interface to support hardware mipmap generation. PIPE_CAP_GENERATE_MIPMAP is added to allow a driver to specify if this new interface is supported; if not supported, the state tracker will fallback to mipmap generation by rendering/texturing. v2: add PIPE_CAP_GENERATE_MIPMAP to the disabled section for all drivers v3: add format to the generate_mipmap interface to allow mipmap generation using a format other than the resource format v4: fix return type of trace_context_generate_mipmap() Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]> Reviewed-by: Jose Fonseca <[email protected]>
* gallium/radeon: implement PIPE_CAP_INVALIDATE_BUFFERNicolai Hähnle2016-01-141-1/+1
| | | | Reviewed-by: Marek Olšák <[email protected]>
* gallium: add PIPE_CAP_INVALIDATE_BUFFERNicolai Hähnle2016-01-141-0/+1
| | | | | | | | | It makes sense to re-use pipe->invalidate_resource for the purpose of glInvalidateBufferData, but this function is already implemented in vc4 where it doesn't have the expected behavior. So add a capability flag to indicate that the driver supports the expected behavior. Reviewed-by: Marek Olšák <[email protected]>
* gallium: add PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENTIlia Mirkin2016-01-081-0/+1
| | | | | Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* gallium: add PIPE_SHADER_CAP_MAX_SHADER_BUFFERSIlia Mirkin2016-01-081-0/+1
| | | | | Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* gallium: add caps for POSITION and FACE system valuesMarek Olšák2016-01-081-0/+2
| | | | | | | v2: document the integer behavior Reviewed-by: Edward O'Callaghan <[email protected] Reviewed-by: Brian Paul <[email protected]>
* radeon, si: Use TGSI chan name defines in lp_build_emit_fetch() callsEdward O'Callaghan2016-01-081-1/+1
| | | | | Signed-off-by: Edward O'Callaghan <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium: add caps to expose support for multi indirect drawsIlia Mirkin2016-01-071-0/+2
| | | | | Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* gallium/r600: Replace ALIGN_DIVUP with DIV_ROUND_UPKrzysztof Sobiecki2016-01-063-3/+2
| | | | | | | | ALIGN_DIVUP is a driver specific(r600g) macro that duplicates DIV_ROUND_UP functionality. Replacing it with DIV_ROUND_UP eliminates this problems. Signed-off-by: Krzysztof A. Sobiecki <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/drivers/r600: Use unsigned for loop indexEdward O'Callaghan2016-01-061-9/+9
| | | | | | Found-by: Coccinelle Signed-off-by: Edward O'Callaghan <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* gallium/drivers: Remove unnecessary semicolonsEdward O'Callaghan2016-01-061-1/+1
| | | | | | Found-by: Coccinelle Signed-off-by: Edward O'Callaghan <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* gallium/radeon: dump LLVM module outside of radeon_llvm_compileMarek Olšák2016-01-031-1/+3
| | | | | Reviewed-by: Edward O'Callaghan <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/radeon: always add +DumpCode to the LLVM target machine for LLVM <= 3.5Marek Olšák2016-01-031-1/+1
| | | | | | | It's the same behavior that we use for later LLVM. Reviewed-by: Edward O'Callaghan <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/radeon: r600_can_dump_shader should get TGSI processor type directlyMarek Olšák2016-01-031-2/+4
| | | | | Reviewed-by: Edward O'Callaghan <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium: add PIPE_CAP_TGSI_PACK_HALF_FLOAT to indicate UP2H/PK2H supportIlia Mirkin2016-01-031-0/+1
| | | | | | Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Edward O'Callaghan <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]>
* gallium/radeon: pass pipe_debug_callback into radeon_llvm_compile (v2)Nicolai Hähnle2016-01-024-5/+9
| | | | | | | This will allow us to send shader debug info via the context's debug callback. Reviewed-by: Edward O'Callaghan <[email protected]> (v1) Reviewed-by: Marek Olšák <[email protected]>
* u_upload_mgr: pass alignment to u_upload_data manuallyMarek Olšák2016-01-021-3/+3
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* u_upload_mgr: pass alignment to u_upload_alloc manuallyMarek Olšák2016-01-021-1/+1
| | | | | | | | | | The fixed alignment of u_upload_mgr will go away. This is the first step. The motivation is that one u_upload_mgr can have multiple users, each allocating from the same buffer, but requiring a different alignment. Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium: add PIPE_CAP_DRAW_PARAMETERSIlia Mirkin2015-12-301-0/+1
| | | | | | | | This allows the state tracker to know that the various draw parameters are available in vertex shaders. Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]>
* r600: fix constant buffer size programmingGrazvydas Ignotas2015-12-292-2/+2
| | | | | | | | | | | | When buffer size is less than 16, zero ends up being programmed as size, which prevents the hardware from fetching the correct values. Fix it by combining shift and align so that the value is always rounded up. Cc: "11.1 11.0 10.6" <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92229 Signed-off-by: Grazvydas Ignotas <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* r600: fix viewport clipping handling (v2)Dave Airlie2015-12-223-12/+15
| | | | | | | | | | | | | | If oViewport is written, vertex reuse need to be turned off. If oViewport is constant, vertex reuse is fine, and VPORT_PROVOKE_DISABLE need to be set. (we don't have enough info to program VPORT_PROVOKE). Fixes: arb_viewport_array-render-viewport-2 and some CTS tests. v2: drop vport provoke write, drop initial state writing this on evergreen, only program it on evergreen. Signed-off-by: Dave Airlie <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* r600: drop VTX_CNT_EN write from initial stateDave Airlie2015-12-221-8/+4
| | | | | | | we always program this in shader stages atom now. Reviewed-by: Marek Olšák <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* gallium/radeon: remove radeon_winsys_cs_handleMarek Olšák2015-12-116-15/+13
| | | | | | | | "radeon_winsys_cs_handle *cs_buf" is now equivalent to "pb_buffer *buf". Reviewed-by: Nicolai Hähnle <[email protected]> Reviewed-by: Edward O'Callaghan <[email protected]> Reviewed-by: Michel Dänzer <[email protected]>
* r600g: remove a Hyper-Z workaround that's likely not needed anymoreMarek Olšák2015-12-111-19/+7
| | | | | | FORCE_OFF == 0, no need to set that Reviewed-by: Alex Deucher <[email protected]>
* r600g: re-enable Hyper-Z for stencil on Evergreen & CaymanMarek Olšák2015-12-111-4/+1
| | | | Reviewed-by: Alex Deucher <[email protected]>
* gallium/radeon: fix Hyper-Z hangs by programming PA_SC_MODE_CNTL_1 correctlyMarek Olšák2015-12-111-2/+7
| | | | | | | | | | This is the recommended setting according to hw people and it makes Hyper-Z stable. Just the two magic states. This fixes Evergreen, Cayman, SI, CI, VI (using the Cayman code). Cc: 11.0 11.1 <[email protected]> Reviewed-by: Alex Deucher <[email protected]>
* r600g: write all MRTs only if there is exactly one output (fixes a hang)Marek Olšák2015-12-111-1/+2
| | | | | | | | This fixes a hang in piglit/arb_blend_func_extended-fbo-extended-blend-pattern_gles2 on REDWOOD. Cc: 11.0 11.1 <[email protected]> Reviewed-by: Alex Deucher <[email protected]>
* r600: add missing return value check.Dave Airlie2015-12-111-0/+2
| | | | | | Pointed out by coverity scan. Signed-off-by: Dave Airlie <[email protected]>
* r600: handle geometry dynamic input array indexDave Airlie2015-12-091-2/+11
| | | | | | | | | | | This fixes: glsl-1.50/execution/geometry/dynamic_input_array_index.shader_test my profanity. We need to load the AR register with the value from the index reg Cc: "11.0 11.1" <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* r600g: fix geom shader input indirect indexing.Dave Airlie2015-12-091-2/+30
| | | | | | | | | | This fixes: gs-input-array-vec4-index-rd The others run out of gprs unfortunately. Cc: "11.0 11.1" <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* r600g: fix outputing to non-0 buffers for stream 0.Dave Airlie2015-12-091-2/+4
| | | | | | | | | | | | | This fixes: arb_transform_feedback3-ext_interleaved_two_bufs_gs arb_transform_feedback3-ext_interleaved_two_bufs_gs_max transform-feedback-builtins If we are only emitting one ring, then emit all output buffers on it. Cc: "11.0 11.1" <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* r600: Add ARB_copy_image supportEdward O'Callaghan2015-12-091-1/+1
| | | | | | | | [airlied: update relnotes] Reviewed-by: Marek Olšák <[email protected]> Signed-off-by: Edward O'Callaghan <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* r600g: allow copying between compatible un/compressed formatsEdward O'Callaghan2015-12-091-1/+2
| | | | | | | | | | | | See: `commit e82c527f1fc2f8ddc64954ecd06b0de3cea92e93` which is where a block in src maps to a pixel in dst and vice versa. e.g. DXT1 <-> R32G32_UINT DXT5 <-> R32G32B32A32_UINT Reviewed-by: Marek Olšák <[email protected]> Signed-off-by: Edward O'Callaghan <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* r600: apply SIMD workaround to cayman also.Dave Airlie2015-12-071-1/+8
| | | | | | | | | | | At last on ARUBA this is required to stop tessellation hanging in heaven. This removes one of the SIMDs from use by the HS/LS. Reviewed-by: Edward O'Callaghan <[email protected]> Tested-by: Edward O'Callaghan <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* r600: fix regression introduced with ring emit changes.Dave Airlie2015-12-071-1/+2
| | | | This was adding one after a CUT which broke end primitive
* r600: remove stale tessellation commentDave Airlie2015-12-071-1/+0
| | | | | | pointed out by Marek. Signed-off-by: Dave Airlie <[email protected]>
* r600: enable tessellation for evergreen/cayman (v2)Dave Airlie2015-12-071-1/+9
| | | | | | | | | | This enables tessellation for evergreen/cayman, This will need changes before committing depending on what hw works etc. working are CAYMAN/REDWOOD/BARTS/TURKS/SUMO/CAICOS v2: only enable on evergreen and above.
* r600g: reduce number of ps thread on caicosDave Airlie2015-12-071-1/+1
| | | | | | this allows tess apps to start Signed-off-by: Dave Airlie <[email protected]>
* r600g: adjust ls/hs thread counts for sumoDave Airlie2015-12-071-4/+4
| | | | | | these stop tess hangs here. Signed-off-by: Dave Airlie <[email protected]>
* r600/asm: enable nstack check for tess ctrl/eval shaders.Dave Airlie2015-12-071-1/+1
| | | | | | | This just makes sure they register at least one stack usage frame like vertex shaders. Signed-off-by: Dave Airlie <[email protected]>
* r600/asm: handle lds read operations.Dave Airlie2015-12-071-1/+21
| | | | | | | | | Reads from the queue shouldn't be merged for now read operations. Reads from the queue shouldn't be merged for now, or put in T slots. Signed-off-by: Dave Airlie <[email protected]>
* r600/asm: add LDS ops and barrier to the once per group restriction.Dave Airlie2015-12-071-1/+1
| | | | | | | LDS ops must be scheduled in X slot, and barrier should be on its own in a group. Signed-off-by: Dave Airlie <[email protected]>
* r600: move VGT_VTX_CNT_EN into shader stages atom.Dave Airlie2015-12-071-2/+2
| | | | | | This should be enabled for tessellation shaders as well. Signed-off-by: Dave Airlie <[email protected]>
* r600: enable tcs/tes dumping for R600_DUMP_SHADERS.Dave Airlie2015-12-071-1/+1
| | | | | | Trivial patch just to enable dumping more. Signed-off-by: Dave Airlie <[email protected]>
* r600: handle SIMD allocation issue with HS/LSDave Airlie2015-12-071-0/+5
| | | | | | | | | At least one SIMD must be kept away from the HS/LS stages in order to avoid a hw issue on evergreen/cayman. This patch implements this workaround. Signed-off-by: Dave Airlie <[email protected]>
* r600/shader: increase number of inputs/outputs to 64.Dave Airlie2015-12-071-2/+2
| | | | | | Tessellation exceeds these sometimes, so increase them for now. Signed-off-by: Dave Airlie <[email protected]>
* r600: handle barrier opcode.Edward O'Callaghan2015-12-071-2/+17
| | | | | | | This handles the barrier opcode for EG/CM. Signed-off-by: Edward O'Callaghan <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* r600/shader: handle tess related system-values.Dave Airlie2015-12-071-2/+148
| | | | | | | | | | This adds handling for TESSINNER/TESSOUTER in the TES where they need to be fetched from LDS, and TESSCOORD which comes in via r0. It also handle primitive ID and invocation ID. Signed-off-by: Dave Airlie <[email protected]>
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