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path: root/src/gallium/drivers/r600
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* gallium: set PIPE_CAP_MIXED_COLORBUFFER_FORMATS in some driversMarek Olšák2011-04-011-0/+1
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* r600g: implement texture barrierFredrik Höglund2011-03-294-0/+12
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* r600g: implement the pipe_screen fence functionsFredrik Höglund2011-03-293-0/+174
| | | | | | v2: Allocate the fences from a single shared buffer object. v3: Allocate the r600_fence structs in blocks of 16. Spin a few times before calling sched_yield in r600_fence_finish().
* r600g: Handle texture fetch instructions with relative addressingFabian Bieler2011-03-271-0/+1
| | | | Signed-off-by: Henri Verbeet <[email protected]>
* r600g: Handle texture fetch instructions with neg or abs on source registerFabian Bieler2011-03-271-3/+5
| | | | Signed-off-by: Henri Verbeet <[email protected]>
* r600g: Handle texture fetch instructions with swizzle on source registerFabian Bieler2011-03-271-10/+20
| | | | Signed-off-by: Henri Verbeet <[email protected]>
* r600g: Check for relative addressing in destination register when trying to ↵Fabian Bieler2011-03-221-1/+8
| | | | | | merge instruction groups Signed-off-by: Henri Verbeet <[email protected]>
* r600g: FLT_TO_INT_FLOOR and FLT_TO_INT_RPI are vector-only instructions on ↵Henri Verbeet2011-03-151-3/+6
| | | | | | Evergreen. Signed-off-by: Henri Verbeet <[email protected]>
* r600g: don't set per-MRT blend bits on R600Alex Deucher2011-03-141-5/+10
| | | | | | | | | It doesn't support them. Also, we shouldn't be emitting CB_BLENDx_CONTROL on R600 as the regs don't exist there, but I'm not sure of the best way to deal with this in the current r600 winsys. Signed-off-by: Alex Deucher <[email protected]>
* r600g: Original R600 does not support per-MRT blendsAlex Deucher2011-03-141-2/+11
| | | | | | Only rv6xx+ support them. Signed-off-by: Alex Deucher <[email protected]>
* r600g: Properly update MULTIWRITE_ENABLE in r600_pipe_shader_ps().Henri Verbeet2011-03-142-8/+7
| | | | | | | This sort of worked because blend state setup cleared MULTIWRITE_ENABLE again, but that's not something we want to depend on. Signed-off-by: Henri Verbeet <[email protected]>
* r600g: Fix the DB_SHADER_CONTROL mask in create_ds_state().Henri Verbeet2011-03-142-10/+8
| | | | Signed-off-by: Henri Verbeet <[email protected]>
* r600g: Properly update DB_SHADER_CONTROL in evergreen_pipe_shader_ps().Henri Verbeet2011-03-141-18/+14
| | | | | | | Disable Z_EXPORT / STENCIL_EXPORT / KILL_ENABLE again if a shader doesn't use those. This is similar to 0a6f09a76a416b8672e149c520aa5bef33174223. Signed-off-by: Henri Verbeet <[email protected]>
* r600g: Move fetch shader register setup to r600_state.c / evergreen_state.c.Henri Verbeet2011-03-146-31/+32
| | | | Signed-off-by: Henri Verbeet <[email protected]>
* r600g: Move r600_pipe_shader_ps() to r600_state.c.Henri Verbeet2011-03-143-95/+97
| | | | Signed-off-by: Henri Verbeet <[email protected]>
* r600g: Move r600_pipe_shader_vs() to r600_state.c.Henri Verbeet2011-03-143-49/+49
| | | | | | | | The idea behind this is that anything touching registers should be in r600_state.c or evergreen_state.c. This is also consistent with evergreen_pipe_shader_vs(). Signed-off-by: Henri Verbeet <[email protected]>
* r600g: Evergreen add support for log opcode.Rafael Monica2011-03-141-1/+1
| | | | Signed-off-by: Henri Verbeet <[email protected]>
* r600g: Only update DB_SHADER_CONTROL once in r600_pipe_shader_ps().Mathias Fröhlich2011-03-131-16/+13
| | | | | | | | | Avoid setting the same gpu register several times in a r600_pipe_state. Compute the final value of the register and set that one time. This avoids some overhead in r600_context_pipe_state_set(). Signed-off-by: Mathias Fröhlich <[email protected]> Signed-off-by: Henri Verbeet <[email protected]>
* r600g: Fix VS sampler view offsets for r600/r700.Carl-Philip Hänsch2011-03-121-1/+2
| | | | | | 077c448d184799e0d9ec962013ec784c6a5c1807 missed this. Signed-off-by: Henri Verbeet <[email protected]>
* r600g: Fix an unused variable warning.Henri Verbeet2011-03-121-3/+5
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* r600g: revert unintentional commitAdam Jackson2011-03-111-1/+0
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* r600: Build fixAdam Jackson2011-03-111-0/+1
| | | | r600_dri.so.tmp: undefined reference to `_mesa_rgba_logicop_enabled'
* gallium: remove flags from the flush functionMarek Olšák2011-03-113-4/+4
| | | | | | | | | | The drivers have been changed so that they behave as if all of the flags were set. This is already implicit in most hardware drivers and required for multiple contexts. Some state trackers were also abusing the PIPE_FLUSH_RENDER_CACHE flag to decide whether flush_frontbuffer should be called. New flag ST_FLUSH_FRONT has been added to st_api.h as a replacement.
* gallium: remove the geom_flags param from is_format_supportedMarek Olšák2011-03-112-4/+3
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* gallium: kill is_resource_referencedMarek Olšák2011-03-113-19/+0
| | | | Only st/xorg used it and even incorrectly with regards to pipelined transfers.
* r600g: remove some now unneeded code from r600_bc_vtx_buildChristian König2011-03-091-25/+1
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* r600g: R700+ can do more than 8 tex and vtx clause in one CF instChristian König2011-03-091-2/+20
| | | | Reviewed-by: Henri Verbeet <[email protected]>
* r600g: split R600 and R700 CF generation for VTX and TEXChristian König2011-03-093-4/+22
| | | | Reviewed-by: Henri Verbeet <[email protected]>
* r600g: set start instance correctlyChristian König2011-03-081-1/+1
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* r600g: Simplify some swizzle lookups.Henri Verbeet2011-03-071-75/+14
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* r600g: Constant buffers can contain up to 4096 constants.Henri Verbeet2011-03-072-1/+2
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* r600g: use long long integers for instance addr calculationChristian König2011-03-061-1/+1
| | | | | | | Using a long for instance addr calculation isn't big enough on 32bit systems, use a long long int instead. Thanks to Rafael Monica for fixing this.
* gallium: split CAP_INSTANCE_DRAWING into INSTANCEID and INSTANCE_DIVISORMarek Olšák2011-03-051-1/+2
| | | | | | | | ARB_instanced_arrays is a subset of D3D9. ARB_draw_instanced is a subset of D3D10. The point of this change is to allow D3D9-level drivers to enable ARB_instanced_arrays without ARB_draw_instanced.
* r600g: simplify instance addr calculationChristian König2011-03-051-47/+4
| | | | | Use MULHI_UINT instead of the more complex INT_TO_FLT->MUL->TRUNC->FLT_TO_INT
* r600g: fix fragment shader size calculationChristian König2011-03-051-8/+9
| | | | | bc.ndw is altered in r600_bc_build, respect that in fragment shader size calculation.
* r600g: disable tiling by default again.Dave Airlie2011-03-041-4/+4
| | | | | | we still have a lot of corner cases that aren't working. Signed-off-by: Dave Airlie <[email protected]>
* r600g: correct mega_fetch_count in fetch shaderChristian König2011-03-031-1/+1
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* r600g: change the cross over point for 2d->1dDave Airlie2011-03-021-1/+1
| | | | | | | this fixes some rendering in the fbo-generatemipmap-formats test on my rv610. Signed-off-by: Dave Airlie <[email protected]>
* r600g: add NV_conditional_render support.Dave Airlie2011-03-014-1/+37
| | | | | | | | This is reliant on a drm patch that I posted on the list + a version bump. These will appear in drm-next today. Signed-off-by: Dave Airlie <[email protected]>
* r600g: start using drm minor version to enable things.Dave Airlie2011-03-018-13/+26
| | | | | | | | | | If the drm minor version is > 9 (i.e. whats in drm-next), we enable s3tc + texture tiling by default now. this changes R600_FORCE_TILING to R600_TILING which can be set to false to disable tiling on working drm. Signed-off-by: Dave Airlie <[email protected]>
* r600g: truncate point sampled texture coordinatesAlex Deucher2011-02-282-1/+14
| | | | | | | | | | | | By default the hardware rounds texcoords. However, for point sampled textures, the expected behavior is to truncate. When we have point sampled textures, set the truncate bit in the sampler. Should fix: https://bugs.freedesktop.org/show_bug.cgi?id=25871 Signed-off-by: Alex Deucher <[email protected]>
* r600g: add missing evergreen INT_TO_FLT to r600_bc_get_num_operandsAlex Deucher2011-02-281-0/+1
| | | | Signed-off-by: Alex Deucher <[email protected]>
* r600g: indentation fixesJerome Glisse2011-02-286-66/+65
| | | | Signed-off-by: Jerome Glisse <[email protected]>
* r600g: implement instanced drawing supportChristian König2011-02-286-103/+191
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* Revert "r600g: Don't negate result of ABS instruction"Dave Airlie2011-02-281-2/+0
| | | | | | This reverts commit b6d40213935da702570eca2c0861bd4b1d7f5254. This actually breaks gears here on my rv670.
* r600g: Process TRUNC with tgis_op2Fabian Bieler2011-02-281-2/+2
| | | | | | TRUNC is neither a scalar instruction nor exclusive to the Trans unit. Signed-off-by: Dave Airlie <[email protected]>
* r600g: Don't negate result of ABS instructionFabian Bieler2011-02-281-0/+2
| | | | Signed-off-by: Dave Airlie <[email protected]>
* r600g: explicity set sign bits for RGTCDave Airlie2011-02-251-2/+4
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* r600g: bc 4/5 or rgtc textures need to be tiled as well.Dave Airlie2011-02-252-10/+10
| | | | | | Make the s3tc upload code more generic. Signed-off-by: Dave Airlie <[email protected]>
* r600g: EXT_texture_array support.Dave Airlie2011-02-246-9/+39
| | | | | | | | | | | This adds EXT_texture_array support to r600g, it passes the piglit array-texture test but I suspect may not be complete. It currently requires a kernel patch to fix the CS checker to allow these, so you need to use R600_ARRAY_TEXTURE=true for now to enable them. Signed-off-by: Dave Airlie <[email protected]>
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