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path: root/src/gallium/drivers/r600
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* r600/eg: make sure we allow vpm bit on other CF ops.Dave Airlie2018-02-011-0/+1
* r600/sb: just add some missing debug bitsDave Airlie2018-02-011-0/+15
* r600: fix buffer resinfo opcode translation.Dave Airlie2018-02-012-2/+2
* gallium: introduce PIPE_CAP_FENCE_SIGNAL v2Andres Rodriguez2018-01-301-0/+1
* r600/sb: insert the else clause when we might depart from a loopDave Airlie2018-01-311-0/+17
* r600: add ARB_query_buffer_object supportDave Airlie2018-01-2910-31/+817
* r600/shader: refactor mul hi/lo instruction emissionDave Airlie2018-01-291-254/+116
* r600/eg: construct proper rat mask for image/buffers.Dave Airlie2018-01-293-8/+30
* autotools: include meson build files in tarballDylan Baker2018-01-191-1/+2
* r600: enable ARB_enhanced_layoutsDave Airlie2018-01-191-1/+1
* r600/sb: add lds related peepholes.Dave Airlie2018-01-181-1/+8
* r600/sb: use different stacks for tracking lds and queue usage.Dave Airlie2018-01-182-3/+24
* r600/sb: schedule LDS ops in appropriate places.Dave Airlie2018-01-182-0/+7
* r600/sb: hit the scheduler with a big hammer to avoid lds splits.Dave Airlie2018-01-181-0/+3
* r600/sb: adding lds oq tracking to the schedulerDave Airlie2018-01-182-3/+15
* r600/sb: add gcm support to avoid clause between lds read/queue readDave Airlie2018-01-182-2/+17
* r600/sb: handle lds special dest registers.Dave Airlie2018-01-182-2/+2
* r600/sb: handle LDS operations in folding.Dave Airlie2018-01-181-0/+11
* r600/sb: add finalising for lds output queue special values.Dave Airlie2018-01-181-0/+12
* r600/sb: add initial support for parsing lds operations.Dave Airlie2018-01-181-2/+50
* r600/sb: disable if conversion for hsDave Airlie2018-01-181-1/+1
* r600/sb: lds ops have no dst register.Dave Airlie2018-01-181-1/+1
* r600/sb: introduce special register values for lds support.Dave Airlie2018-01-183-1/+33
* r600/sb: update last_cf if alu is the last clauseDave Airlie2018-01-181-0/+1
* r600/sb: start adding GDS supportDave Airlie2018-01-1813-13/+123
* r600/sb: add tess/compute initial state registers.Dave Airlie2018-01-181-1/+4
* r600/sb: fix a bug emitting ar load from a constant.Dave Airlie2018-01-181-0/+3
* r600/shader: only emit add instruction if param has a value.Dave Airlie2018-01-181-6/+8
* r600: emit 0 gds_op for tf write.Dave Airlie2018-01-181-2/+3
* r600: add support for ARB_shader_clock.Dave Airlie2018-01-183-5/+29
* gallium: remove PIPE_CAP_USER_CONSTANT_BUFFERSMarek Olšák2018-01-171-1/+0
* gallium: remove PIPE_CAP_TEXTURE_SHADOW_MAPMarek Olšák2018-01-171-1/+0
* gallium: remove PIPE_CAP_TWO_SIDED_STENCILMarek Olšák2018-01-171-1/+0
* r600/shader: Initialize max_driver_temp_used correctly for the first timeGert Wollny2018-01-151-0/+1
* r600: don't emit tes samplers/views when tes isn't activeRoland Scheidegger2018-01-102-0/+19
* r600: increase number of UBOs to 15Roland Scheidegger2018-01-103-22/+37
* r600: use GET_BUFFER_RESINFO vtx fetch on eg instead of setting up constsRoland Scheidegger2018-01-104-58/+50
* r600: increase number of ubos by one to 14Roland Scheidegger2018-01-104-4/+9
* r600: set up constants needed for txq for buffers and cube maps with tesRoland Scheidegger2018-01-101-0/+16
* r600: don't emit reloc for ring buffer out into the blueRoland Scheidegger2018-01-102-8/+6
* r600: hack up num_render_backends on Juniper to 8Roland Scheidegger2018-01-101-2/+19
* r600: fix enabled_rb_mask on eg/cmRoland Scheidegger2018-01-101-2/+9
* r600: fix sampler indexing with texture buffers samplingRoland Scheidegger2018-01-102-2/+4
* r600: don't use vtx offset for load_sample_positionRoland Scheidegger2018-01-101-1/+1
* r600: drop l2 related queriesDave Airlie2018-01-103-18/+0
* r600/shader: only read back the necessary tess factor components.Dave Airlie2018-01-101-4/+4
* meson: set opencl flags for r600Dylan Baker2018-01-081-2/+5
* r600: fix textureSize queries with tbosRoland Scheidegger2017-12-302-24/+33
* r600: kill off native_integer shader ctx flagRoland Scheidegger2017-12-301-18/+0
* r600: fix atomic counter index mode getting emitted on pre-caymanDave Airlie2017-12-271-1/+1