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* r600g: add framebuffer support for 2/10/10/10 integerDave Airlie2011-11-272-0/+4
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* r600g: add int support for 2/10/10/10 format.Dave Airlie2011-11-271-0/+3
| | | | | | integer wasn't set properly for the non-uniform types. Signed-off-by: Dave Airlie <[email protected]>
* android: pass -std=c99 by defaultChia-I Wu2011-11-261-2/+0
| | | | | Several modules expect a C99 compiler already. It is also the default for Makefile build.
* r600g: handle all remaining CAPsMarek Olšák2011-11-221-0/+6
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* r600g: remove default case statements in get_paramMarek Olšák2011-11-221-9/+3
| | | | This will throw a compile warning if there's an unhandled CAP.
* u_vbuf_mgr: rename to u_vbufMarek Olšák2011-11-223-4/+4
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* gallium: separate out floating-point CAPs into its own enumMarek Olšák2011-11-221-7/+8
| | | | | | | | | | | | | | | The motivation behind this is to add some self-documentation in the code about how each CAP can be used. The idea is: - enum pipe_cap is only valid in get_param - enum pipe_capf is only valid in get_paramf Which CAPs are floating-point have been determined based on how everybody except svga implemented the functions. svga have been modified to match all the other drivers. Besides that, the floating-point CAPs are now prefixed with PIPE_CAPF_.
* gallium: remove PIPE_CAP_GLSL and enable GLSL unconditionallyMarek Olšák2011-11-221-1/+0
| | | | | Only i965g does not enable GLSL, but that driver has been unmaintained and bitrotting for quite a while anyway.
* r600g: handle PIPE_SHADER_CAP_OUTPUT_READVadim Girlin2011-11-211-0/+2
| | | | Signed-off-by: Vadim Girlin <[email protected]>
* r600g: use u_vbuf_mgr to set/get the index bufferMarek Olšák2011-11-202-14/+5
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* r600g: set MIN/MAX_VTX_INDX to 0 and ~0, respectivelyMarek Olšák2011-11-201-10/+4
| | | | | | | The CS checker doesn't check the regs and the state-tracker-provided values are not to be trusted. This also removes the hack for non-zero index bias.
* r600g: don't change the order of writes in merge_inst_groupVadim Girlin2011-11-171-1/+14
| | | | | | | | | | | | | | Merge may produce incorrect order of operations for r600-eg: x: inst1 R0.x, ... ; //from current group ... t: inst0 R0.x, ... ; //from previous group, same destination Result of inst1 will be lost. So compare destinations and don't allow this. Signed-off-by: Vadim Girlin <[email protected]>
* r600g: fix the representation of control-flow instructionsMarek Olšák2011-11-159-426/+536
| | | | | | | | | | | | | | | | | | | | | | | | | | We need something that looks like a compiler and not like some hacker put some functions together. /rant This is a band-aid for these two problems: - The R600 and EG control-flow instructions appear in switch statements next to each other, causing conflicts when adding new instructions. - The ALU control-flow instructions are bitshifted by 3 (from CF_INST 26:29 to CF_INST 23:29, as is defined by r600 ISA) even for EG, where CF_INST is 22:29. To fix this mess, the 'inst' field is bitshifted to the left either by 22, 23, or 26 (directly in the definitions), such that it can be just or'd when making bytecode without any shifting. All switch statements have been divided into two, one for R600 and the other for EG. Of course, there is a better way to do this, but that is left for future work. Tested on RV730 and REDWOOD with no regressions. v2: minor cleanup as per Alex's comment. Reviewed-by: Alex Deucher <[email protected]>
* r600g: mask write for fake VS export componentsVadim Girlin2011-11-141-4/+4
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* r600g: fix op3 & write in merge_inst_groupsVadim Girlin2011-11-141-1/+1
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* r600g: set max max tex/vtx instructions count to 16 for caymanAlex Deucher2011-11-141-3/+1
| | | | | | Cayman is 16 as well. Signed-off-by: Alex Deucher <[email protected]>
* r600g: set max tex/vtx instructions count to 16 for evergreenVadim Girlin2011-11-141-1/+1
| | | | | | | According to evergreen-isa doc 16 is max value for evergreen. More than 16 doesn't work for me. Signed-off-by: Vadim Girlin <[email protected]>
* r600g: properly handle cayman in is_alu_vec_unit_inst()Alex Deucher2011-11-131-7/+15
| | | | Signed-off-by: Alex Deucher <[email protected]>
* r600g: fix cb offset for flushed_depth_textureVadim Girlin2011-11-131-1/+1
| | | | Signed-off-by: Vadim Girlin <[email protected]>
* r600g: fix stencil buffer ref counting on evergreenVadim Girlin2011-11-131-1/+4
| | | | Signed-off-by: Vadim Girlin <[email protected]>
* r600g: lazy load for AR registerVadim Girlin2011-11-133-46/+61
| | | | | | Emit MOVA* instruction only when AR is used. Signed-off-by: Vadim Girlin <[email protected]>
* r600g: include INTERP_[XY|ZW] in is_alu_vec_unit_instVadim Girlin2011-11-131-1/+3
| | | | | | This will disallow moving them to the trans slot in merge_inst_groups Signed-off-by: Vadim Girlin <[email protected]>
* r600g: don't set the query result to 0 after a call to get_query_resultMarek Olšák2011-11-111-2/+0
| | | | get_query_result doesn't reset the result. Only begin_query does.
* r600g: the type of OCCLUSION_PREDICATE result should be booleanMarek Olšák2011-11-113-11/+17
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* r600g: implement PIPE_QUERY_OCCLUSION_PREDICATEMarek Olšák2011-11-101-5/+21
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* r600g: remove useless texture barrierMarek Olšák2011-11-101-2/+0
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* r600g: flush the whole context when CS is full, not just hw_contextMarek Olšák2011-11-103-1/+6
| | | | Because we disable render condition in r600_flush, but not in r600_context_flush.
* r600g: turn some CS overflow checks into assertionsMarek Olšák2011-11-102-12/+2
| | | | They're not really exhaustive and not so useful either.
* r600g: put the rest of CS overflow checks in r600_need_cs_spaceMarek Olšák2011-11-103-18/+9
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* r600g: flush caches regardless of render conditionMarek Olšák2011-11-101-5/+5
| | | | What if somebody enables render condition just before we flush...
* r600g: disable render condition at the end of CS, re-enable at the beginningMarek Olšák2011-11-102-0/+19
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* r600g: don't suspend queries if they have already been suspended by blitterMarek Olšák2011-11-101-2/+11
| | | | And add some assertions.
* r600g: properly reserve CS space for queries_suspendMarek Olšák2011-11-103-21/+18
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* r600g: reserve CS space for a draw command in begin_query and render_conditionMarek Olšák2011-11-103-11/+25
| | | | There's no point in emitting those if you can't emit a draw command too.
* r600g: consolidate checking whether CS is fullMarek Olšák2011-11-103-31/+28
| | | | | | This adds a new function r600_need_cs_space. Currently, it's easy to overflow the CS - queries are not counted in. I guess that's not the only case where the driver may crap out.
* r600g: clarify meaning of one variable in shader codegenMarek Olšák2011-11-091-1/+1
| | | | It's easier to read now.
* r600g: cosmetic changes in query codeMarek Olšák2011-11-092-10/+7
| | | | Mainly updating comments and removing one use of a magic number.
* r600g: use modulo for computing index into query (ring) buffersMarek Olšák2011-11-091-14/+5
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* r600g: make r600_query_result more genericMarek Olšák2011-11-091-15/+37
| | | | | We'll soon start adding new query types, maybe even querying more than one value per query.
* r600g: add initial linestipple support.Dave Airlie2011-11-066-6/+51
| | | | | | | It seems line loop stipple in hardware needs something I don't know, it might need a proper geometry shader who knows. Signed-off-by: Dave Airlie <[email protected]>
* r600g: move SPI setup to PS setupVadim Girlin2011-11-054-74/+73
| | | | | | | | | | | | | | | | | | | | | | SPI semantic indices for PS/VS are now static, so we don't need to update spi config for every shaders combination. We can move the functionality of r600_spi_update to r600(evergreen)_pipe_shader_ps. Flatshade state is now controlled by the global FLAT_SHADE_ENA flag instead of updating FLAT_SHADE for all inputs. Sprite coord still requires the update of spi setup when sprite_coord_enable is first changed from zero (enabled), and then only when it's changed to other non-zero value (enabled for other input). Change to zero (disabling) and back to the same value is handled via global SPRITE_COORD_ENA. New field "sprite_coord_enable" added to "struct r600_pipe_shader" to track current state for the pixel shader. It's checked in the r600_update_derived_state. Signed-off-by: Vadim Girlin <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* r600g: precalculate semantic indices for SPI setupVadim Girlin2011-11-055-58/+65
| | | | | | | | | | There is no need to duplicate semantic mapping which is done in hw, so get rid of r600_find_vs_semantic_index. TGSI name/sid pair is mapped to the 8-bit semantic index for SPI. Signed-off-by: Vadim Girlin <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* Revert "r600g: precalculate semantic indices for SPI setup"Alex Deucher2011-11-045-64/+57
| | | | | | This reverts commit c15f8569fddac5f8aee77863922fd5bb992cfe8a. This breaks r6xx.
* Revert "r600g: move SPI setup to PS setup"Alex Deucher2011-11-044-73/+74
| | | | | | This reverts commit 9804cf3118ae7249098af2a9c78b36f4fb576ee4. This breaks r6xx.
* r600g: move SPI setup to PS setupVadim Girlin2011-11-044-74/+73
| | | | | | | | | | | | | | | | | | | | | SPI semantic indices for PS/VS are now static, so we don't need to update spi config for every shaders combination. We can move the functionality of r600_spi_update to r600(evergreen)_pipe_shader_ps. Flatshade state is now controlled by the global FLAT_SHADE_ENA flag instead of updating FLAT_SHADE for all inputs. Sprite coord still requires the update of spi setup when sprite_coord_enable is first changed from zero (enabled), and then only when it's changed to other non-zero value (enabled for other input). Change to zero (disabling) and back to the same value is handled via global SPRITE_COORD_ENA. New field "sprite_coord_enable" added to "struct r600_pipe_shader" to track current state for the pixel shader. It's checked in the r600_update_derived_state. Signed-off-by: Vadim Girlin <[email protected]>
* r600g: precalculate semantic indices for SPI setupVadim Girlin2011-11-045-57/+64
| | | | | | | | | There is no need to duplicate semantic mapping which is done in hw, so get rid of r600_find_vs_semantic_index. TGSI name/sid pair is mapped to the 8-bit semantic index for SPI. Signed-off-by: Vadim Girlin <[email protected]>
* r600g: more integer supportDave Airlie2011-11-032-23/+37
| | | | | | just some more trivial integer changes for r600/r700. Signed-off-by: Dave Airlie <[email protected]>
* r600g: add comment about special shader exportsAlex Deucher2011-11-021-0/+32
| | | | | | | | | Certain exports (position, point size, etc.) are treated specially by the shader and not counted as generic exports. Note the exports and any relevant related state bits. Signed-off-by: Alex Deucher <[email protected]>
* r600g: take into account PSIZE output for spi mappingVadim Girlin2011-11-021-3/+6
| | | | | | | | | | | | Skip PSIZE and POSITION when counting VS outputs. Fixes https://bugs.freedesktop.org/show_bug.cgi?id=42435 Tested without regressions on evergreen. NOTE: this is a candidate for the 7.11 branch. Signed-off-by: Vadim Girlin <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* r600g: reset the render condition to NULL when rendering unconditionallyMarek Olšák2011-10-301-1/+5
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