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* gallium: Replace gl_rasterization_rules with lower_left_origin and ↵José Fonseca2013-04-232-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | half_pixel_center. Squashed commit of the following: commit 04c5fa2cbb8e89d6f2fa5a75af1cca03b1f6b852 Author: José Fonseca <[email protected]> Date: Tue Apr 23 17:37:18 2013 +0100 gallium: s/lower_left_origin/bottom_edge_rule/ commit 4dff4f64fa83b9737def136fffd161d55e4f1722 Author: José Fonseca <[email protected]> Date: Tue Apr 23 17:35:04 2013 +0100 gallium: Move diagram to docs. commit 442a63012c8c3c3797f45e03f2ca20ad5f399832 Author: James Benton <[email protected]> Date: Fri May 11 17:50:55 2012 +0100 gallium: Replace gl_rasterization_rules with lower_left_origin and half_pixel_center. This change is necessary to achieve correct results when using OpenGL FBOs. Reviewed-by: Marek Olšák <[email protected]>
* r600g: initialize CMASK and HTILE with the GPU using streamoutMarek Olšák2013-04-234-7/+80
| | | | | | | | | | | | | This fixes a crash when a resource cannot be mapped to the CPU's address space because it's too big. This puts a global pipe_context in r600_screen, which is guarded by a mutex, so that we can use pipe_context when there isn't one around. Hopefully our multi-context support is solid. Reviewed-by: Alex Deucher <[email protected]> NOTE: This is a candidate for the 9.1 branch.
* r600/llvm: Read stacksize from config headerVincent Lejeune2013-04-233-2/+4
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* /bin/bash: q : commande introuvableVincent Lejeune2013-04-231-1/+1
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* st/mesa: optionally apply texture swizzle to border color v2Christoph Bumiller2013-04-181-0/+3
| | | | | | | | | | | | This is the only sane solution for nv50 and nvc0 (really, trust me), but since on other hardware the border colour is tightly coupled with texture state they'd have to undo the swizzle, so I've added a cap. The dependency of update_sampler on the texture updates was introduced to avoid doing the apply_depthmode to the swizzle twice. v2: Moved swizzling helper to u_format.c, extended the CAP to provide more accurate information.
* r600g: Fix build with --enable-openclTom Stellard2013-04-181-1/+2
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* r600g/llvm: Use gprcount from llvmVincent Lejeune2013-04-173-1/+4
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* gallium: Disambiguate TGSI_OPCODE_IF.José Fonseca2013-04-171-8/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | TGSI_OPCODE_IF condition had two possible interpretations: - src.x != 0.0f - Mesa statetracker when PIPE_SHADER_CAP_INTEGERS was false either for vertex and fragment shaders - gallivm/llvmpipe - postprocess - vl state tracker - vega state tracker - most old drivers - old internal state trackers - many graw examples - src.x != 0U - Mesa statetracker when PIPE_SHADER_CAP_INTEGERS was true for both vertex and fragment shaders - tgsi_exec/softpipe - r600 - radeonsi - nv50 And drivers that use draw module also were a mess (because Mesa would emit float IFs, but draw module supports native integers so it would interpret IF arg as integers...) This sort of works if the source argument is limited to float +0.0f or +1.0f, integer 0, but would fail if source is float -0.0f, or integer in the float NaN range. It could also fail if source is integer 1, and hardware flushes denormalized numbers to zero. But with this change there are now two opcodes, IF and UIF, with clear meaning. Drivers that do not support native integers do not need to worry about UIF. However, for backwards compatibility with old state trackers and examples, it is advisable that native integer capable drivers also support the float IF opcode. I tried to implement this for r600 and radeonsi based on the surrounding code. I couldn't do this for nouveau, so I just shunted IF/UIF together, which matches the current behavior. Reviewed-by: Roland Scheidegger <[email protected]> Reviewed-by: Marek Olšák <[email protected]> v2: - Incorporate Roland's feedback. - Fix r600_shader.c merge conflict. - Fix typo in radeon, spotted by Michel Dänzer. - Incorporte Christoph Bumiller's patch to handle TGSI_OPCODE_IF(float) properly in nv50/ir.
* gallium: Eliminate TGSI_OPCODE_IFC.José Fonseca2013-04-171-3/+6
| | | | | | Never used or implemented. Reviewed-by: Roland Scheidegger <[email protected]>
* r600/uvd: cleanup disabling tiling on pre EG asicsChristian König2013-04-161-5/+6
| | | | | | Set transfer flag instead of fiddling with the tilling params directly. Signed-off-by: Christian König <[email protected]>
* r600g: Workaround for a harware bug with nested loops on CaymanMartin Andersson2013-04-161-3/+15
| | | | | | | | | | | | | | | | There is a hardware bug on Cayman where a BREAK/CONTINUE followed by LOOP_STARTxxx for nested loops may put the branch stack into a state such that ALU_PUSH_BEFORE doesn't work as expected. Workaround this by replacing the ALU_PUSH_BEFORE with a PUSH + ALU Fixes piglit tests EXT_transform_feedback/order* v2: Use existing loop count and improve comment v3: [Vadim Girlin] Set jump address for PUSH instructions NOTE: This is a candidate for the 9.1 branch Signed-off-by: Vadim Girlin <[email protected]>
* r600g: implement pipeline statistics queryMarek Olšák2013-04-164-1/+100
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* winsys/radeon: use query_value for timestamp, remove query_timestampMarek Olšák2013-04-161-1/+1
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* r600g: add a debug flag for printing virtual addresses of resourcesMarek Olšák2013-04-164-0/+17
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* r600g: add a query returning the amount of time spent during bo_map sync.Marek Olšák2013-04-163-0/+11
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* radeon/llvm: Use a struct for storing compiled codeTom Stellard2013-04-151-2/+6
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* r600g: add get_sample_position support (v3)Dave Airlie2013-04-112-122/+240
| | | | | | | v2: I rewrote this to use the sample positions properly. v3: rewrite properly to use bitfield to cast back to signed ints Signed-off-by: Dave Airlie <[email protected]>
* r600g: fix two issues in compressed msaa reading codeDave Airlie2013-04-111-2/+2
| | | | | | | | | I've no idea when sample_chan would ever be 4 here, but 4 is most definitely wrong, array textures have it as 3 as well. Also the cayman code though unused is obviously wrong. Signed-off-by: Dave Airlie <[email protected]>
* radeon/uvd: add UVD implementation v5Christian König2013-04-115-6/+212
| | | | | | | | | | | | | | Just everything you need for UVD with r600g and radeonsi. v2: move UVD code to radeon subdir, clean up build system additions, remove an unused SI function, disable tiling on SI for now. v3: some minor indentation fix and rebased v4: dpb size calculation fixed v5: implement proper fall-back in case the kernel doesn't support UVD, based on patches from Andreas Boll but cleaned up a bit more. Signed-off-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]>
* r600g: Add support for GL_ARB_texture_buffer_rangeFredrik Höglund2013-04-113-5/+11
| | | | Reviewed-by: Marek Olšák <[email protected]>
* r600g: fix valgrind warning on CaymanMarek Olšák2013-04-101-1/+1
| | | | Warning: "Conditional jump or move depends on uninitialised value(s)".
* r600g: Fix UMAD on CaymanMartin Andersson2013-04-091-13/+32
| | | | | | | | | | | | The multiplication part of tgsi_umad did not work on Cayman, because it did not populate the correct vector slots. This fixed hardlocks in the EXT_transform_feedback/order tests. NOTE: This is a candidate for the stable branches. (might not be easy to cherry-pick though) Signed-off-by: Marek Olšák <[email protected]>
* r600g/llvm: Add support for native isa for pre EGVincent Lejeune2013-04-081-1/+5
| | | | | This fixes bug 62756 : https://bugs.freedesktop.org/show_bug.cgi?id=62756#c12
* gallium: PIPE_COMPUTE_CAP_IR_TARGET - allow drivers to specify a processor v2Tom Stellard2013-04-054-69/+72
| | | | | | | | | | | | This target string now contains four values instead of three. The old processor field (which was really being interpreted as arch) has been split into two fields: processor and arch. This allows drivers to pass a more a more detailed description of the hardware to compiler frontends. v2: - Adapt to libclc changes Reviewed-by: Francisco Jerez <[email protected]>
* r600g/llvm: Workaround for wrong tex.offset_*Vincent Lejeune2013-04-041-0/+3
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* r600g/llvm: Do not override llvm provided stack_sizeVincent Lejeune2013-04-031-1/+2
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* r600g/llvm: Do not change cf_alu inst when adding alusVincent Lejeune2013-04-031-7/+2
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* gallium: add PIPE_CAP_QUERY_PIPELINE_STATISTICSChristoph Bumiller2013-04-031-0/+1
| | | | Reviewed-by: Marek Olšák <[email protected]>
* r600g: don't reserve more stack space than required v5Vadim Girlin2013-04-023-56/+142
| | | | | | | | | | | Reduced stack size allows to run more threads in some cases, improving performance for the shaders that use stack (that is, for the shaders with control flow instructions). E.g. with unigine-based apps. v4: implement exact computation taking into account wavefront size v5: add cases for RV620, RS880 Signed-off-by: Vadim Girlin <[email protected]>
* r600g: fix range handling for tgsi input declarations v2Vadim Girlin2013-04-021-3/+7
| | | | Signed-off-by: Vadim Girlin <[email protected]>
* radeon/llvm: move system value fetching to common codeChristian König2013-04-021-12/+0
| | | | | | | | This should be used by both SI and R600. Signed-off-by: Christian König <[email protected]> Reviewed-by: Michel Dänzer <[email protected]> Tested-by: Michel Dänzer <[email protected]>
* r600g/llvm: Use stack_size provided from llvm.Vincent Lejeune2013-04-011-0/+1
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* r600g/llvm: uses function attribute to pass shader typeVincent Lejeune2013-04-011-0/+1
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* r600g/llvm: Add support for cf_alu native encodeVincent Lejeune2013-04-013-1/+16
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* r600g/llvm: use native encode for texVincent Lejeune2013-03-311-23/+27
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* r600g: add a driver query returning the amount of requested VRAM and GTT memoryMarek Olšák2013-03-263-0/+21
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* r600g: add a driver query returning the number of draw_vbo callsMarek Olšák2013-03-264-5/+65
| | | | between begin_query and end_query
* r600g: fix crash while binding a NULL constant bufferMarek Olšák2013-03-261-1/+1
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* r600g: Use virtual address for PIPE_QUERY_SO* in r600_emit_query_endMartin Andersson2013-03-251-2/+3
| | | | | | | | | | | | Virtual address is used for PIPE_QUERY_SO* queries in r600_emit_query_begin, but not in r600_emit_query_end. This will trigger a GPU fault when one of those queries is made and virtual address is enabled. Note: this is a candidate for the 9.1 branch Signed-off-by: Alex Deucher <[email protected]>
* gallium,st/mesa: don't use blit-based transfers with software rasterizersMarek Olšák2013-03-231-0/+1
| | | | | | | | | The blit-based paths for TexImage, GetTexImage, and ReadPixels aren't very fast with software rasterizer. Now Gallium drivers have the ability to turn them off. Reviewed-by: Brian Paul <[email protected]> Tested-by: Brian Paul <[email protected]>
* r600g: Honour legacy debugging environment variablesMichel Dänzer2013-03-221-0/+10
| | | | | | | | This helps minimize confusion / effort when moving between branches or helping others. Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* gallium: add TGSI_SEMANTIC_TEXCOORD,PCOORD v3Christoph Bumiller2013-03-201-0/+2
| | | | | | | | | | | | | | | This makes it possible to identify gl_TexCoord and gl_PointCoord for drivers where sprite coordinate replacement is restricted. The new PIPE_CAP_TGSI_TEXCOORD decides whether these varyings should be hidden behind the GENERIC semantic or not. With this patch only nvc0 and nv30 will request that they be used. v2: introduce a CAP so other drivers don't have to bother with the new semantic v3: adapt to introduction gl_varying_slot enum
* r600g: don't emit SQ_DYN_GPR_RESOURCE_LIMIT_1 on caymanAlex Deucher2013-03-191-1/+0
| | | | | | | | | Doesn't exist on the asic and will cause a CS rejection if VM is disabled. Note: this is a candidate for the 9.1 branch. Signed-off-by: Alex Deucher <[email protected]>
* r600g: emit DB_SRESULTS_COMPARE_STATE0 on r6xx/r7xxAlex Deucher2013-03-192-1/+3
| | | | | | Not using HiS yet, but matches what we do on evergreen+. Signed-off-by: Alex Deucher <[email protected]>
* tgsi: use separate structure for indirect address v2Christian König2013-03-191-1/+1
| | | | | | | | | | | | | | To further improve the optimization of source and destination indirect addressing we need the ability to store a reference to the declaration of the addressed operands. Since most of the fields in tgsi_src_register doesn't apply for an indirect addressing operand replace it with a separate tgsi_ind_register structure and so make room for extra information. v2: rename Declaration to ArrayID, put the ArrayID into () instead of [] Signed-off-by: Christian König <[email protected]>
* r600g: properly set non_disp tiling mode for DMA (v2)Alex Deucher2013-03-171-2/+6
| | | | | | | | | Needs to be set for depth, stencil, and fmask just like other blocks. v2: drop additional cayman bits for now Signed-off-by: Alex Deucher <[email protected]>
* r600g: Use blitter rather than DMA for 128bpp on cayman (v3)Alex Deucher2013-03-171-0/+11
| | | | | | | | | | | | | | | | | | | | | On cayman, 128bpp surfaces require non_disp ordering for hw access to both linear and tiled surfaces. When we use the 3D engine we can set the non_disp ordering on both the tiled and linear sides (via CB or texture), but when we use the DMA engine, we can only set the non_disp ordering on the tiled side, so after a L2T operation with the DMA engine, the data ends up in the wrong order on the tiled side. v2: cayman/TN only v3: fix comments Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=60802 Note: this is a candidate for the 9.1 branch. Signed-off-by: Alex Deucher <[email protected]>
* r600g/llvm: Move llvm wrapper functions into the radeon directoryTom Stellard2013-03-135-90/+4
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* mesa: Use PACKAGE_BUGREPORT macro.Matt Turner2013-03-121-1/+1
| | | | Reviewed-by: Eric Anholt <[email protected]>
* r600g/llvm: Fix buildTom Stellard2013-03-111-1/+1
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