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* r600g/compute: Add more debugging outputTom Stellard2012-07-112-1/+42
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* r600g: improve flushed depth texture handling v2Vadim Girlin2012-07-116-61/+83
| | | | | | | | | | | Use r600_resource_texture::flished_depth_texture for GPU access, and allocate it in the VRAM. For transfers we'll allocate texture in the GTT and store it in the r600_transfer::staging. Improves performance when flushed depth texture is frequently used by the GPU, e.g. in Lightsmark (~30%) Signed-off-by: Vadim Girlin <[email protected]>
* gallium: add QUERY_TIMESTAMP cap and get_timestamp screen functionMarek Olšák2012-07-101-0/+1
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* r600g: Don't create a texture for the memory_pool during screen initTom Stellard2012-07-092-8/+24
| | | | | | | This fixes a segfault in r600_screen_create() introduced by eb065f5d9d1159af3a88a64a7606c9b6d67dc3 Reported by tilman on irc.
* r600g: Update number of gprs when adding a vertex instructionTom Stellard2012-07-091-0/+4
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* r600g/compute: Use evergreen_cb() for binding RATsTom Stellard2012-07-095-70/+48
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* r600g: Add support for RATs in evergreen_cb()Tom Stellard2012-07-091-3/+11
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* r600g: Use a texture as the underlying resource for compute_memory_poolTom Stellard2012-07-092-18/+37
| | | | This the first step towards being able to use evergreen_cb to bind RATs.
* r600g: Add is_rat flag to r600_resource_textureTom Stellard2012-07-091-0/+1
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* r600g: Add r600_context_pipe_state_emit()Tom Stellard2012-07-092-6/+71
| | | | | | | | This function is used when dispatching compute shader in order to avoid mixing compute and 3D registers in the context's dirty list. This allows the compute code to resuse 3D functions like evergreen_cb, which return a struct r600_pipe_state and still have control over when and how the register writes are emitted.
* r600g: Add pkt_flag parameter to r600_context_block_emit_dirty()Tom Stellard2012-07-093-3/+15
| | | | | | | This allows the shader type bit to be set in the pm4 header when emitting registers for compute shaders. Reviewed-by: Marek Olšák <[email protected]>
* r600g/compute: Move LOOP_CONST initialization to start_compute_cs atomTom Stellard2012-07-091-14/+16
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* r600g: Add start_compute_cs atom to struct r600_contextTom Stellard2012-07-094-94/+96
| | | | | | | | | The start_compute_cs atom initializes some config and context registers to the values needed for running compute shaders. When a compute shader is dispatched, this atom is emitted after the start_cs_cmd atom, which initializes registers that are common to both 3D and compute. Reviewed-by: Marek Olšák <[email protected]>
* r600g: Add pkt_flag member to struct r600_command_bufferTom Stellard2012-07-091-3/+16
| | | | | | | | | | Some packets require the shader type bit (bit 1) to be set when used for compute shaders. The pkt_flag will be initialized to RADEON_CP_PACKET3_COMPUTE_MODE for any struct r600_command_buffer used for dispatching compute shaders and it will be or'd against the result of the PKT3 macro when adding a new packet to a struct r600_command buffer. Reviewed-by: Marek Olšák <[email protected]>
* r600g: Only emit start_cs_cmd atom once for compute command streamsTom Stellard2012-07-091-2/+0
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* r600g: fix stencil texturing with Z32_FLOAT_S8X24_UINTMarek Olšák2012-07-091-0/+2
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* r600g: add assertions after translate_colorswap/colorformat/dbformat/texformatMarek Olšák2012-07-092-3/+17
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* r600g: inline r600_hw_copy_regionMarek Olšák2012-07-091-21/+5
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* r600g: enable dual src blending on r7xxMarek Olšák2012-07-091-1/+1
| | | | No lockups here.
* r600g: use depth format from pipe_surface, not pipe_resourceMarek Olšák2012-07-092-4/+4
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* r600g: use u_box_origin_2d helper functionMarek Olšák2012-07-091-10/+3
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* r600g: remove stray semicolonMarek Olšák2012-07-071-1/+1
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* radeon/llvm: Emit raw ISA for vertex fetch instructionsTom Stellard2012-06-291-20/+40
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* r600g: enable DUAL_EXPORT mode when possible on r6xx/r7xxJerome Glisse2012-06-273-18/+57
| | | | | | | DUAL_EXPORT can be enabled on r6xx/r7xx when all CBs use 16-bit export and there is no depth/stencil export. Signed-off-by: Jerome Glisse <[email protected]>
* r600g: enable DUAL_EXPORT mode when possibleVadim Girlin2012-06-274-6/+55
| | | | | | | | It seems DUAL_EXPORT on evergreen may be enabled when all CBs use 16-bit export mode (EXPORT_4C_16BPC), also there should be at least one CB, and the PS shouldn't export depth/stencil. Signed-off-by: Vadim Girlin <[email protected]>
* r600g: avoid unnecessary shader exports v2Vadim Girlin2012-06-276-28/+41
| | | | | | | | | | | | In some cases TGSI shader has more color outputs than the number of CBs, so it seems we need to limit the number of color exports. This requires different shader variants depending on the nr_cbufs, but on the other hand we are doing less exports, which are very costly. v2: fix various piglit regressions Signed-off-by: Vadim Girlin <[email protected]> Signed-off-by: Jerome Glisse <[email protected]>
* r600g: cache shader variants instead of rebuilding v3Vadim Girlin2012-06-275-94/+217
| | | | | | | | | | | | | | | | | | | Shader variants are stored in the list, the key for lookup is based on the states that require different hw shaders - currently it's rctx->two_side (all gpus) and rctx->nr_cbufs (evergreen/cayman, when writes_all property is set). v2: - use simple list instead of keymap as suggested by Marek on irc - call r600_adjust_gprs from r600_bind_vs_shader for r6xx/r7xx (r600_shader_select isn't used for vertex shaders currently) v3: - fix call to r600_adjust_gprs - do it after updating current shader Improves performance for some apps, e.g. FlightGear - see https://bugs.freedesktop.org/show_bug.cgi?id=50360 Signed-off-by: Vadim Girlin <[email protected]>
* r600g: don't disable streamout if it hasn't been startedMarek Olšák2012-06-261-1/+1
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* r600g: inline r600_blit_push_depth and use resource_copy_regionMarek Olšák2012-06-253-18/+11
| | | | | We are going to have a separate resource for depth texturing and transfers and this is just a transfer thing.
* r600g: split flushed depth texture creation and flushingMarek Olšák2012-06-255-16/+34
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* r600g: Unify SURFACE_SYNC packet emission for 3D and computeTom Stellard2012-06-213-101/+30
| | | | | | Drop the compute specific evergreen_set_buffer_sync() function and instead use the r600_surface_sync_command atom for emitting SURFACE_SYNC packets.
* r600g: Enable reusing of compute stateTom Stellard2012-06-211-6/+9
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* r600g: Fix reading vtx instruction offset from bytestreamTom Stellard2012-06-211-1/+1
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* make: Fold ASM_CFLAGS into DEFINES.Eric Anholt2012-06-211-1/+0
| | | | | | Every place that uses ASM_FLAGS already uses DEFINES. Not including it in DEFINES is just a way to screw up potential users, as I've done several times while working on the build system.
* r600g: fix z/stencil texture creation v2Jerome Glisse2012-06-191-15/+17
| | | | | | | | | | z or stencil texture should not be created with the z/stencil flags for surface creation as they are intended to be bound as texture. v2: remove broken code Signed-off-by: Jerome Glisse <[email protected]>
* gallium: Add PIPE_CAP_START_INSTANCEFredrik Höglund2012-06-191-0/+1
| | | | Reviewed-by: Brian Paul <[email protected]>
* r600g: enable streamout by default on r7xx and DRM 2.17.0Marek Olšák2012-06-173-8/+16
| | | | | | Now that it's in Linus's tree. Has anyone had a chance to test streamout on Cayman recently?
* r600g: fix lockups with streamout on r7xxMarek Olšák2012-06-152-0/+15
| | | | | | | | | This requires the latest streamout kernel patches. Streamout is disabled by default on r7xx, so this patch is safe for regular users. Reviewed-by: Alex Deucher <[email protected]>
* r600g: compute CS space for streamout correctly, add commentsMarek Olšák2012-06-151-6/+7
| | | | | | SET_CONTEXT_REG was not counted in. Reviewed-by: Alex Deucher <[email protected]>
* r600g: set SMX_ACTION_ENA to fix streamout cache flushes on some chipsetsMarek Olšák2012-06-151-1/+2
| | | | | | It helps on R7xx. Reviewed-by: Alex Deucher <[email protected]>
* winsys/radeon: enable IB submission to compute rings v2Christian König2012-06-151-1/+1
| | | | | | | | | | | This allows to submit things to the compute only rings on cayman+ v2: rebased on current master and actually make use of the new flag in evergreen_compute.c Signed-off-by: Christian König <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* r600g: Compute support for CaymanTom Stellard2012-06-064-18/+51
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* radeon/llvm: Emit 2 bytes for vertex fetch offsetsTom Stellard2012-06-011-0/+2
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* r600g: compute support for evergreenAdam Rak2012-06-0120-12/+2674
| | | | | | | | | Tom Stellard: - Updated for gallium interface changes - Fixed a few bugs: + Set the loop counter + Calculate the correct number of pipes - Added hooks into the LLVM compiler
* r600g: handle R16G16B16_FLOAT and R32G32B32_FLOAT in translate_colorswapKai Wasserbäch2012-05-251-0/+2
| | | | | | Fixes https://bugs.freedesktop.org/show_bug.cgi?id=50318 Signed-off-by: Kai Wasserbäch <[email protected]>
* Revert "r600g: set round_mode to truncate and get rid of tgsi_f2i on evergreen"Vadim Girlin2012-05-252-6/+56
| | | | | | | | | | | | This reverts commit 60bf0f05b472e66bf1175fcec7a274dab6f7e2a3. It seems round_mode behaves differently in some cases depending on the instruction/slot. Reverting it for now. Fixes https://bugs.freedesktop.org/show_bug.cgi?id=50232 Signed-off-by: Vadim Girlin <[email protected]> Reviewed-by: Tom Stellard <[email protected]>
* radeon/llvm: fix sampler index in llvm_emit_texVadim Girlin2012-05-251-2/+4
| | | | | | | | | | Sampler index isn't a second source operand for some tgsi texture instructions. Let's assume it's always the last. Fixes https://bugs.freedesktop.org/show_bug.cgi?id=50230 Signed-off-by: Vadim Girlin <[email protected]> Reviewed-by: Tom Stellard <[email protected]>
* r600g: add RECIP_INT, PRED_SETE_INT to r600_bytecode_get_num_operandsVadim Girlin2012-05-251-0/+2
| | | | | | | | Fixes https://bugs.freedesktop.org/show_bug.cgi?id=50315 Signed-off-by: Vadim Girlin <[email protected]> Tested-by: Kai Wasserbäch <[email protected]> Reviewed-by: Tom Stellard <[email protected]>
* r600g: Handle MUL_IEEE in r600_bytecode_get_num_operandsTom Stellard2012-05-171-0/+2
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* gallium/radeon: Fix r300g tiling breakage.Michel Dänzer2012-05-161-0/+1
| | | | | | Commit 11f056a3f0b87e86267efa8b5ac9d36a343c9dc1 broke the r300g build. Fix it up, and reinstate some code which isn't needed by r600g and radeonsi but is by r300g.
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