| Commit message (Collapse) | Author | Age | Files | Lines |
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This fixes piglit/fbo-blit-stretched.
Reviewed-by: Alex Deucher <[email protected]>
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Reviewed-by: Alex Deucher <[email protected]>
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Reviewed-by: Alex Deucher <[email protected]>
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Reviewed-by: Alex Deucher <[email protected]>
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Reviewed-by: Alex Deucher <[email protected]>
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Tested on RS880, Evergreen and Cayman.
Reviewed-by: Alex Deucher <[email protected]>
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Let's use the shader key describing the state.
Reviewed-by: Alex Deucher <[email protected]>
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Signed-off-by: Alex Deucher <[email protected]>
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Compute shaders fetch data from vertex buffers via the texture cache, so
we need to make sure the texture cache is flushed.
v2:
- Fix rebase mistake
- Fix spelling in comment
Reviewed-by: Marek Olšák <[email protected]>
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LOOP_START_DX10 ignores the LOOP_CONFIG* registers, so it is not limited
to 4096 iterations like the other LOOP_* instructions. Compute shaders
need to use this instruction, and since we aren't optimizing loops with
the LOOP_CONFIG* registers for pixel and vertex shaders, it seems like
we should just use it for everything.
Reviewed-by: Marek Olšák <[email protected]>
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For buffers (which is what is being used for RATs), the
COLOR*_DIM.WIDTH_MASK field needs to be set to the low 16-bits of the
buffer size, and the COLOR*_DIM.HEIEGHT_MAX needs to be set to the
high bits.
Reviewed-by: Marek Olšák <[email protected]>
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The kernel CS checker will fail if this register is not initialized.
Reviewed-by: Marek Olšák <[email protected]>
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Reviewed-by: Marek Olšák <[email protected]>
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Signed-off-by: Tom Stellard <[email protected]>
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No regressions found in the tests of opencl-example/run_tests.sh.
Signed-off-by: Xinya Zhang <[email protected]>
Signed-off-by: Tom Stellard <[email protected]>
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to allow stencil-only sampler-only formats (like X24S8)
NOTE: This is a candidate for the stable branches.
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Seems to have an affect on the allowable range of
values. Set evergreen+ to 1/256 to match 6xx/7xx.
fixes:
https://bugs.freedesktop.org/show_bug.cgi?id=54877
Signed-off-by: Alex Deucher <[email protected]>
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It kills performance if the resource is linear.
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v2: Group vgt register together to avoid lockup
v3: Split multi primitive register and index bias register
v4: Bump R600_NUM_ATOMS
Signed-off-by: Marek Olšák <[email protected]>
Signed-off-by: Jerome Glisse <[email protected]>
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Reviewed-by: Jerome Glisse <[email protected]>
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Reviewed-by: Jerome Glisse <[email protected]>
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Reviewed-by: Jerome Glisse <[email protected]>
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Reviewed-by: Jerome Glisse <[email protected]>
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Reviewed-by: Jerome Glisse <[email protected]>
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Reviewed-by: Jerome Glisse <[email protected]>
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Reviewed-by: Jerome Glisse <[email protected]>
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Reviewed-by: Jerome Glisse <[email protected]>
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Reviewed-by: Jerome Glisse <[email protected]>
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by reusing the CS initialization in r600_context_flush.
Reviewed-by: Jerome Glisse <[email protected]>
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Reviewed-by: Jerome Glisse <[email protected]>
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Reviewed-by: Jerome Glisse <[email protected]>
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Update only those sampler states which are changed in a shader stage,
instead of always updating all sampler states in the shader stage.
That requires keeping a bitmask of those states which are enabled, and those
states which are dirty at a given point (subset of enabled states).
This is similar to how sampler views, constant buffers, and vertex buffers
are handled.
Reviewed-by: Jerome Glisse <[email protected]>
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Reviewed-by: Jerome Glisse <[email protected]>
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Reviewed-by: Jerome Glisse <[email protected]>
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to easily and robustly handle multiple shader stages
Reviewed-by: Jerome Glisse <[email protected]>
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Reviewed-by: Jerome Glisse <[email protected]>
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Reviewed-by: Jerome Glisse <[email protected]>
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Based on the patch called "simplify and fix flushing and synchronization"
by Jerome Glisse.
Rebased, removed unneded code, simplified more and cleaned up.
Also, SH_ACTION_ENA is not set when changing shaders (hw doesn't seem
to need it). It's only used to flush constant buffers.
Reviewed-by: Jerome Glisse <[email protected]>
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Previous command stream might have set any of the constant buffer
and the previous address might no longer be valid thus GPU might
preload constant from random invalid address and possibly triggering
lockup.
Signed-off-by: Jerome Glisse <[email protected]>
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To avoid GPU lockup registers must be emited in a specific order
(no kidding ...). This patch rework atom emission so order in which
atom are emited in respect to each other is always the same. We
don't have any informations on what is the correct order so order
will need to be infered from fglrx command stream.
v2: add comment warning that atom order should not be taken lightly
v3: rebase on top of alphatest atom fix
Signed-off-by: Jerome Glisse <[email protected]>
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Signed-off-by: Jerome Glisse <[email protected]>
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This patch has been generated by the following Coccinelle semantic
patch:
// Remove useless checks for NULL before freeing
//
// free (NULL) is a no-op, so there is no need to avoid it
@@
expression E;
@@
+ free (E);
+ E = NULL;
- if (unlikely (E != NULL)) {
- free(E);
(
- E = NULL;
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- E = 0;
)
...
- }
@@
expression E;
type T;
@@
+ free ((T) E);
+ E = NULL;
- if (unlikely (E != NULL)) {
- free((T) E);
(
- E = NULL;
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- E = 0;
)
...
- }
@@
expression E;
@@
+ free (E);
- if (unlikely (E != NULL)) {
- free (E);
- }
@@
expression E;
type T;
@@
+ free ((T) E);
- if (unlikely (E != NULL)) {
- free ((T) E);
- }
Reviewed-by: Brian Paul <[email protected]>
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This patch has been generated by the following Coccinelle semantic
patch:
// Don't cast the return value of malloc/realloc.
//
// Casting the return value of malloc/realloc only stands to hide
// errors.
@@
type T;
expression E1, E2;
@@
- (T)
(
_mesa_align_calloc(E1, E2)
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_mesa_align_malloc(E1, E2)
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calloc(E1, E2)
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malloc(E1)
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realloc(E1, E2)
)
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Use 1/256 for R6xx/7xx, 1/4096 for evergreen, instead of default 1/16.
Helps to pass some piglit tests (fbo, multisample).
Signed-off-by: Vadim Girlin <[email protected]>
Reviewed-by: Alex Deucher <[email protected]>
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