| Commit message (Collapse) | Author | Age | Files | Lines |
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Fixes broken glTexImage2D with format=GL_RGBA since
1a339b6c71ebab6e1a64f05b2e133022d3bbcd15
The origin for this behaviour is that r600_is_format_supported
checks only against r600_state_inline.h tables not evergreens.
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Should fix http://bugs.freedesktop.org/show_bug.cgi?id=38566 .
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evergreen+ stores depth and stencil separately so when we
allocate a depth/stencil fbo, make sure we allocate enough
memory for both depth and stencil buffers.
Signed-off-by: Alex Deucher <[email protected]>
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This is equivalent results with less looping.
Signed-off-by: Dave Airlie <[email protected]>
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this drop a bunch of unnecessary checks (i.e. should be trapped
at gallium level), and also removes the switch statement in favour
of some calculated values for the vgt values.
Signed-off-by: Dave Airlie <[email protected]>
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the attached patch should be an improvement over Vadim Girlin's patch
fixing LIT instruction for r600g (commit
2fe39b46e73aea37152777fe11d489e0b1bc3f92).
Instructions used in tgsi_lit have been reordered to always write to a
dst channel after the same channel in src has been read (so if src ==
dst, input values are not overwritten before being used).
Signed-off-by: Dave Airlie <[email protected]>
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st/mesa guarantees that all bound sampler states have the same value
in seamless_cube_map.
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Current LIT implementation uses dst components for storing temp
results, possibly overwriting still needed values (depends on the
swizzles).
This patch uses temp reg for one of such cases (found in etqw) and
fixes "LIT R.z, R.xyzz".
Tested on evergreen. Fixes some etqw-demo rendering glitches when
"Lighting" is set to "High" in the settings.
Signed-off-by: Vadim Girlin <[email protected]>
Signed-off-by: Dave Airlie <[email protected]>
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fixes https://bugs.freedesktop.org/show_bug.cgi?id=36917
Signed-off-by: Vadim Girlin <[email protected]>
Signed-off-by: Dave Airlie <[email protected]>
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Source box needs to be adjusted for blitting from compressed formats.
fixes https://bugs.freedesktop.org/show_bug.cgi?id=35434
Signed-off-by: Vadim Girlin <[email protected]>
Signed-off-by: Dave Airlie <[email protected]>
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Signed-off-by: Vadim Girlin <[email protected]>
Signed-off-by: Dave Airlie <[email protected]>
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[airlied: final chunk of Mike's patch from bug 37476
this uses a loop to emit the GRADIENTS and does a check to
see if we need to fetch to a temporary register. It also
increases the context src gpr to 4 which is needed here.]
Signed-off-by: Dave Airlie <[email protected]>
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[airlied: taken from Mike's patch in bug 37476]
Signed-off-by: Dave Airlie <[email protected]>
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Mike had actually done a lot of the TXD support in a patch in bug
37476 which I see now, I'll add the bits of his work that I didn't think
to add to my work.
Signed-off-by: Dave Airlie <[email protected]>
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This at least passes the piglit arb_shader_texture_lod-texgrad test,
the AMD shader analyzer seems to multiply the V component by an unspecified
constant value no idea why.
Signed-off-by: Dave Airlie <[email protected]>
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This sets the base level as the zero level, which fixes
piglit/texturing/tex-miplevel-selection*.
The r600 hardware ignores the BASE_LEVEL field in some cases, so we can't
use it.
Evergreen might need this too.
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fixes fdo bug 38145
Signed-off-by: Vadim Girlin <[email protected]>
Signed-off-by: Dave Airlie <[email protected]>
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this needs a piglit run.
Signed-off-by: Dave Airlie <[email protected]>
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Put the shader programs into an immutable buffer object.
Also make sure that those object can be taken from the user
space buffer object pool.
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Fix an obvious typo in the yet unused part of the shader setup.
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No regressions found with :
- piglit (quick.tests)
- Unigine Heaven
- Lightsmark
- openarena
- Imprudence (Second Life fork)
agd5f Note: this patch was previously reverted due to piglit
regressions, but I'm not able to reproduce them here.
See this bug:
https://bugs.freedesktop.org/show_bug.cgi?id=34008
and discussion:
http://lists.freedesktop.org/archives/dri-devel/2011-June/011996.html
Signed-off-by: Alex Deucher <[email protected]>
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pipe_resource_reference call was miossing, thus creating massive memory under certain conditions.
Fix : https://bugs.freedesktop.org/show_bug.cgi?id=37168
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Ideally we'd have a compiler and register spilling and all that
but this is good enough for now to avoid the gpu hang in piglit,
glsl-vs-vec4-indexing-temp-dst-in-nested-loop-combined
on r600/r700 cards.
based on r600c patch
Andre Maasikas <[email protected]>
r600c: bump sq gpr resources if a shader needs more than default
Signed-off-by: Dave Airlie <[email protected]>
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GLOBAL_GPR regs should be 0. Need to set the
number of temp regs in SQ_GPR_RESOURCE_MGMT_1.
Signed-off-by: Alex Deucher <[email protected]>
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need more sleep or something.
Signed-off-by: Dave Airlie <[email protected]>
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So only with kernel version 2.7 can this work, thanks to Alex
for pointing that out. Also add a workaround for a hw bug.
Signed-off-by: Dave Airlie <[email protected]>
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Evergreen can do this as well as cayman, so we should enable it.
This fixes a gpu lockup with
glsl-vs-vec4-indexing-temp-dst-in-nested-loop-combined.shader_test
I need to add a better workaround for r600/r700.
Signed-off-by: Dave Airlie <[email protected]>
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Signed-off-by: Dave Airlie <[email protected]>
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Since resources don't generally vary in size, this splits
the emit path, it also takes into a/c that texture and vertex resources
have different number of relocs, and avoids emitting the extra
reloc for vertex resources.
Signed-off-by: Dave Airlie <[email protected]>
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This relies on the reference member being first, so document it.
Signed-off-by: Dave Airlie <[email protected]>
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Not sure why these were included originally.
Signed-off-by: Alex Deucher <[email protected]>
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Wondering why r600g needs to include r300_pci_ids.h
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At the end of flushing we were scanning over 450 blocks
with generally about 50 enabled. This reduces the scanning
to just the list of enabled blocks.
Signed-off-by: Dave Airlie <[email protected]>
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There isn't much point taking the overhead of range/block lookups on resources
we aren't going to be getting resource registers at wierd offsets.
Signed-off-by: Dave Airlie <[email protected]>
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resource setting could be a fair bit more lightweight,
this patch just separates the resource structs from the standard
reg tracking structs in the driver, later patches will improve
the winsys.
Signed-off-by: Dave Airlie <[email protected]>
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This updates the spi state after ps/vs binding or rasteriser state
change.
Signed-off-by: Dave Airlie <[email protected]>
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This is a lot more branch predictor friendly, it actually
showed up in cachegrind profiles.
Signed-off-by: Dave Airlie <[email protected]>
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These are handled separately in the winsys, so don't need the calculations
done at this point. this manifested as a crash in point-sprite,
Thanks to XoD on #radeon for pointing it out.
Signed-off-by: Dave Airlie <[email protected]>
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This modifies the VGT state and move the SPI setup to its own discrete state.
It then just sets the SPI state up and the VGT state up once and modifies
them thereafter.
Signed-off-by: Dave Airlie <[email protected]>
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