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path: root/src/gallium/drivers/r600
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* gallium: PIPE_COMPUTE_CAP_IR_TARGET - allow drivers to specify a processor v2Tom Stellard2013-04-054-69/+72
| | | | | | | | | | | | This target string now contains four values instead of three. The old processor field (which was really being interpreted as arch) has been split into two fields: processor and arch. This allows drivers to pass a more a more detailed description of the hardware to compiler frontends. v2: - Adapt to libclc changes Reviewed-by: Francisco Jerez <[email protected]>
* r600g/llvm: Workaround for wrong tex.offset_*Vincent Lejeune2013-04-041-0/+3
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* r600g/llvm: Do not override llvm provided stack_sizeVincent Lejeune2013-04-031-1/+2
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* r600g/llvm: Do not change cf_alu inst when adding alusVincent Lejeune2013-04-031-7/+2
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* gallium: add PIPE_CAP_QUERY_PIPELINE_STATISTICSChristoph Bumiller2013-04-031-0/+1
| | | | Reviewed-by: Marek Olšák <[email protected]>
* r600g: don't reserve more stack space than required v5Vadim Girlin2013-04-023-56/+142
| | | | | | | | | | | Reduced stack size allows to run more threads in some cases, improving performance for the shaders that use stack (that is, for the shaders with control flow instructions). E.g. with unigine-based apps. v4: implement exact computation taking into account wavefront size v5: add cases for RV620, RS880 Signed-off-by: Vadim Girlin <[email protected]>
* r600g: fix range handling for tgsi input declarations v2Vadim Girlin2013-04-021-3/+7
| | | | Signed-off-by: Vadim Girlin <[email protected]>
* radeon/llvm: move system value fetching to common codeChristian König2013-04-021-12/+0
| | | | | | | | This should be used by both SI and R600. Signed-off-by: Christian König <[email protected]> Reviewed-by: Michel Dänzer <[email protected]> Tested-by: Michel Dänzer <[email protected]>
* r600g/llvm: Use stack_size provided from llvm.Vincent Lejeune2013-04-011-0/+1
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* r600g/llvm: uses function attribute to pass shader typeVincent Lejeune2013-04-011-0/+1
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* r600g/llvm: Add support for cf_alu native encodeVincent Lejeune2013-04-013-1/+16
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* r600g/llvm: use native encode for texVincent Lejeune2013-03-311-23/+27
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* r600g: add a driver query returning the amount of requested VRAM and GTT memoryMarek Olšák2013-03-263-0/+21
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* r600g: add a driver query returning the number of draw_vbo callsMarek Olšák2013-03-264-5/+65
| | | | between begin_query and end_query
* r600g: fix crash while binding a NULL constant bufferMarek Olšák2013-03-261-1/+1
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* r600g: Use virtual address for PIPE_QUERY_SO* in r600_emit_query_endMartin Andersson2013-03-251-2/+3
| | | | | | | | | | | | Virtual address is used for PIPE_QUERY_SO* queries in r600_emit_query_begin, but not in r600_emit_query_end. This will trigger a GPU fault when one of those queries is made and virtual address is enabled. Note: this is a candidate for the 9.1 branch Signed-off-by: Alex Deucher <[email protected]>
* gallium,st/mesa: don't use blit-based transfers with software rasterizersMarek Olšák2013-03-231-0/+1
| | | | | | | | | The blit-based paths for TexImage, GetTexImage, and ReadPixels aren't very fast with software rasterizer. Now Gallium drivers have the ability to turn them off. Reviewed-by: Brian Paul <[email protected]> Tested-by: Brian Paul <[email protected]>
* r600g: Honour legacy debugging environment variablesMichel Dänzer2013-03-221-0/+10
| | | | | | | | This helps minimize confusion / effort when moving between branches or helping others. Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* gallium: add TGSI_SEMANTIC_TEXCOORD,PCOORD v3Christoph Bumiller2013-03-201-0/+2
| | | | | | | | | | | | | | | This makes it possible to identify gl_TexCoord and gl_PointCoord for drivers where sprite coordinate replacement is restricted. The new PIPE_CAP_TGSI_TEXCOORD decides whether these varyings should be hidden behind the GENERIC semantic or not. With this patch only nvc0 and nv30 will request that they be used. v2: introduce a CAP so other drivers don't have to bother with the new semantic v3: adapt to introduction gl_varying_slot enum
* r600g: don't emit SQ_DYN_GPR_RESOURCE_LIMIT_1 on caymanAlex Deucher2013-03-191-1/+0
| | | | | | | | | Doesn't exist on the asic and will cause a CS rejection if VM is disabled. Note: this is a candidate for the 9.1 branch. Signed-off-by: Alex Deucher <[email protected]>
* r600g: emit DB_SRESULTS_COMPARE_STATE0 on r6xx/r7xxAlex Deucher2013-03-192-1/+3
| | | | | | Not using HiS yet, but matches what we do on evergreen+. Signed-off-by: Alex Deucher <[email protected]>
* tgsi: use separate structure for indirect address v2Christian König2013-03-191-1/+1
| | | | | | | | | | | | | | To further improve the optimization of source and destination indirect addressing we need the ability to store a reference to the declaration of the addressed operands. Since most of the fields in tgsi_src_register doesn't apply for an indirect addressing operand replace it with a separate tgsi_ind_register structure and so make room for extra information. v2: rename Declaration to ArrayID, put the ArrayID into () instead of [] Signed-off-by: Christian König <[email protected]>
* r600g: properly set non_disp tiling mode for DMA (v2)Alex Deucher2013-03-171-2/+6
| | | | | | | | | Needs to be set for depth, stencil, and fmask just like other blocks. v2: drop additional cayman bits for now Signed-off-by: Alex Deucher <[email protected]>
* r600g: Use blitter rather than DMA for 128bpp on cayman (v3)Alex Deucher2013-03-171-0/+11
| | | | | | | | | | | | | | | | | | | | | On cayman, 128bpp surfaces require non_disp ordering for hw access to both linear and tiled surfaces. When we use the 3D engine we can set the non_disp ordering on both the tiled and linear sides (via CB or texture), but when we use the DMA engine, we can only set the non_disp ordering on the tiled side, so after a L2T operation with the DMA engine, the data ends up in the wrong order on the tiled side. v2: cayman/TN only v3: fix comments Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=60802 Note: this is a candidate for the 9.1 branch. Signed-off-by: Alex Deucher <[email protected]>
* r600g/llvm: Move llvm wrapper functions into the radeon directoryTom Stellard2013-03-135-90/+4
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* mesa: Use PACKAGE_BUGREPORT macro.Matt Turner2013-03-121-1/+1
| | | | Reviewed-by: Eric Anholt <[email protected]>
* r600g/llvm: Fix buildTom Stellard2013-03-111-1/+1
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* r600g: add debug options disabling various copy-buffer-related featuresMarek Olšák2013-03-113-2/+11
| | | | This will be invaluable for debugging and bug reports.
* r600g: allocate FMASK right after the texture, so that it's aligned with itMarek Olšák2013-03-111-1/+1
| | | | | | This avoids the kernel CS checker errors with MSAA textures. Reviewed-by: Jerome Glisse <[email protected]>
* r600g: remove r600.h, move the stuff elsewhere (mostly to r600_pipe.h)Marek Olšák2013-03-118-167/+126
| | | | Reviewed-by: Jerome Glisse <[email protected]>
* r600g: remove r600_hw_context_priv.h, move the stuff to r600_pipe.hMarek Olšák2013-03-116-46/+13
| | | | Reviewed-by: Jerome Glisse <[email protected]>
* r600g: remove deprecated state management codeMarek Olšák2013-03-1110-560/+2
| | | | | | It's nice to see so much code that did pretty much nothing go away. Reviewed-by: Jerome Glisse <[email protected]>
* r600g: atomize pixel shaderMarek Olšák2013-03-117-207/+83
| | | | Reviewed-by: Jerome Glisse <[email protected]>
* r600g: atomize vertex shaderMarek Olšák2013-03-118-232/+203
| | | | Reviewed-by: Jerome Glisse <[email protected]>
* r600g: inline r600_pipe_shader functionMarek Olšák2013-03-115-58/+51
| | | | | | also change names of other functions, so that they make sense Reviewed-by: Jerome Glisse <[email protected]>
* r600g: dump vertex elements state along with the fetch shaderMarek Olšák2013-03-111-0/+8
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* r600g: remove bytecode dumpingMarek Olšák2013-03-112-240/+0
| | | | Reviewed-by: Tom Stellard <[email protected]>
* r600g: use a single env var R600_DEBUG, disable bytecode dumpingMarek Olšák2013-03-1110-95/+122
| | | | | | | | | | | | | | | | | | | | | | | | | Only the disassembler is used to dump shaders. Here's a few examples how to use R600_DEBUG. Log compute info: R600_DEBUG=compute Dump all shaders: R600_DEBUG=fs,vs,gs,ps,cs Dump pixel shaders only: R600_DEBUG=ps Disable Hyper-Z: R600_DEBUG=nohyperz Disable the LLVM backend: R600_DEBUG=nollvm Or use any combination of the above, or print all options: R600_DEBUG=help Reviewed-by: Tom Stellard <[email protected]>
* r600g: cleanup #include recursion between r600_pipe.h and evergreen_compute.hMarek Olšák2013-03-117-2/+6
| | | | Reviewed-by: Tom Stellard <[email protected]>
* r600g: don't check for R600_ENABLE_S3TC env varMarek Olšák2013-03-111-10/+3
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* radeon/llvm: make SGPRs proper function arguments v2Christian König2013-03-071-0/+1
| | | | | | | v2: remove unrelated changes Signed-off-by: Christian König <[email protected]> Reviewed-by: Tom Stellard <[email protected]>
* r600g/llvm: Update CONSTANT_BUFFER address space definitionChristian König2013-03-071-1/+1
| | | | | | To match recent LLVM changes. Signed-off-by: Christian König <[email protected]>
* r600g: Check comp_mask before merging export instructionsVincent Lejeune2013-03-031-0/+1
| | | | | Fixes a llvm uncovered (rare) bug where consecutive exports were merged even if they have incompatible mask.
* r600g: fix check_and_set_bank_swizzle for caymanVadim Girlin2013-03-031-7/+3
| | | | | Tested-by: Vincent Lejeune <vljn at ovi.com> Reviewed-by: Vincent Lejeune <vljn at ovi.com>
* r600g: enable CP DMA on 6xxAlex Deucher2013-03-011-1/+1
| | | | | | Tested across several 6xx parts, no piglit regressions. Signed-off-by: Alex Deucher <[email protected]>
* r600g: don't require dword alignment with CP DMA for buffer transfersMarek Olšák2013-03-015-11/+9
| | | | | | which is a leftover from the days when we used streamout to copy buffers Tested-by: Andreas Boll <[email protected]>
* r600g: always map uninitialized buffer range as unsynchronizedMarek Olšák2013-03-016-0/+45
| | | | | | | | | | Any driver can implement this simple and efficient optimization. Team Fortress 2 hits it always. The DISCARD_RANGE codepath is not even used with TF2 anymore, so we avoid a ton of useless buffer copies. Tested-by: Andreas Boll <[email protected]> NOTE: This is a candidate for the 9.1 branch.
* r600g: cleanup deprecated register tablesMarek Olšák2013-03-013-45/+14
| | | | | | These registers are either already emitted elsewhere or moved to start_cs. Tested-by: Andreas Boll <[email protected]>
* r600g: unify vgt statesMarek Olšák2013-03-015-26/+9
| | | | | | | The states were split because we thought it caused a hardlock. Now we know the hardlock was caused by something else and has since been fixed. Tested-by: Andreas Boll <[email protected]>
* r600g: flush and invalidate htile cache when appropriateMarek Olšák2013-03-016-1/+21
| | | | | | Tested-by: Andreas Boll <[email protected]> NOTE: This is a candidate for the 9.1 branch.
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