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* r600g: fix CP DMA hazard with index buffer fetches (v3)Marek Olšák2016-06-041-0/+5
| | | | | | | | | v3: use PFP_SYNC_ME on EG-CM only when supported by the kernel, otherwise use MEM_WRITE + WAIT_REG_MEM to emulate that Reviewed-by: Alex Deucher <[email protected]> Tested-by: Grazvydas Ignotas <[email protected]> Tested-by: Dieter Nützel <[email protected]>
* gallium/radeon: clean left-shift undefined behaviorNicolai Hähnle2016-05-071-902/+902
| | | | | | | | | | | | | | Shifting into the sign bit of a signed int is undefined behavior. Unfortunately, there are potentially many places where this happens using the register macros. This commit is the result of running sed -ie "s/(((\(\w\+\)) & 0x\(\w\+\)) << \(\w\+\))/(((unsigned)(\1) \& 0x\2) << \3)/g" on all header files in gallium/{r600,radeon,radeonsi}. Reviewed-by: Marek Olšák <[email protected]>
* r600g: clean up aniso state translationMarek Olšák2016-04-121-3/+5
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* r600g: implement set_active_query_state for pausing occlusion queriesMarek Olšák2016-04-121-0/+1
| | | | | | | Use ZPASS_INCREMENT_DISABLE everywhere. Reviewed-by: Edward O'Callaghan <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* r600g: fix typo in r600 register definitionsMarek Olšák2016-04-121-1/+1
| | | | Acked-by: Edward O'Callaghan <[email protected]>
* r600: do SQ flush ES ring rolling workaroundDave Airlie2015-12-021-0/+1
| | | | | | | | | Need to insert a SQ_NON_EVENT when ever geometry shaders are enabled. Reviewed-by: Marek Olšák <[email protected]> Cc: "10.6 11.0 11.1" <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* r600: consolidate clip state updatesDave Airlie2015-11-301-1/+1
| | | | | | | | Move some common code into one place, tess will also need to use this function. Reviewed-by: Marek Olšák <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* r600g: Pass conservative depth parameters to hwGlenn Kennard2015-11-111-0/+8
| | | | | | | | Supported on R700 and up. Signed-off-by: Glenn Kennard <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* Revert "r600g: Pass conservative depth parameters to hw"Dave Airlie2015-11-111-8/+0
| | | | | | This reverts commit a1fc78911e9a6439db94d6ae91d5672c76e5fb1c. I pushed the wrong patch.
* r600g: Pass conservative depth parameters to hwGlenn Kennard2015-11-111-0/+8
| | | | | | | Supported on R700 and up. Signed-off-by: Glenn Kennard <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* r600: define some values for the fetch constant offsets.Dave Airlie2015-09-121-0/+11
| | | | | | | | This just puts these in one place and #defines them. Reviewed-by: Glenn Kennard <[email protected]> Reviewed-by: Edward O'Callaghan <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* r600g,radeonsi: remove unused ill-formed register field definitionsMarek Olšák2015-08-261-1/+0
| | | | | Acked-by: Christian König <[email protected]> Acked-by: Alex Deucher <[email protected]>
* r600g: Implement GL_ARB_draw_indirect for EG/CMGlenn Kennard2015-02-241-1/+7
| | | | | | | | | | | | | | | | Requires Evergreen/Cayman and radeon kernel module 2.41.0 or newer. Expected piglit fails due to hardware limitations: * arb_draw_indirect-draw-arrays-prim-restart Restarts not applied for DrawArrays commands * arb_draw_indirect-vertexid Base vertex offset is not included in vertex id Marek: bump vgt_state num_dw by 3 (= space needed for one register write) Signed-off-by: Glenn Kennard <[email protected]> Signed-off-by: Marek Olšák <[email protected]>
* r600g: Implement GL_ARB_sample_shadingGlenn Kennard2014-10-121-0/+3
| | | | | | | | Also fixes two sided lighting which was broken at least on pre-evergreen by commit b1eb00. Signed-off-by: Glenn Kennard <[email protected]> Signed-off-by: Marek Olšák <[email protected]>
* r600g: set VGT_ENHANCE=4 on R7xxMarek Olšák2014-09-011-0/+1
| | | | | | | This is a golden setting on RV740, but there is a hw bug which recommends setting it on all R7xx chipsets. Acked-by: Michel Dänzer <[email protected]>
* r600g: copy IA_MULTI_VGT_PARAM programming from radeonsi for CaymanMarek Olšák2014-08-191-0/+11
| | | | | Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Michel Dänzer <[email protected]>
* r600g: use TGSI_PROPERTY to disable viewport and clippingChristoph Bumiller2014-06-021-0/+6
| | | | | | | | | | v2 get rid of magic value, use DEFINES v3 update clip_disable together with vs_position_window_space Big thanks to Marek Olšák! Signed-off-by: David Heidelberger <[email protected]> Signed-off-by: Marek Olšák <[email protected]>
* r600g: fix hang on RV740 by using DX_RASTERIZATION_KILL instead of SX_MISCMarek Olšák2014-04-251-0/+3
| | | | | | | | Changing SX_MISC hangs RV740. When we're at it, let's use DX_RASTERIZATION_KILL on all R700 and later chipsets. Cc: 10.0 10.1 [email protected] Reviewed-by: Alex Deucher <[email protected]>
* r600g: fix for an MSAA hang on RV770Marek Olšák2014-04-251-0/+3
| | | | | Cc: 10.0 10.1 [email protected] Reviewed-by: Alex Deucher <[email protected]>
* r600g: deobfuscate async DMA codeMarek Olšák2014-03-201-0/+1
| | | | Reviewed-by: Michel Dänzer <[email protected]>
* r600g: add support for geom shaders to r600/r700 chipsets (v2)Dave Airlie2014-02-051-1/+49
| | | | | | | | | | | | | This is my first attempt at enabling r600/r700 geometry shaders, the basic tests pass on both my rv770 and my rv635, It requires this kernel patch: http://www.spinics.net/lists/dri-devel/msg52745.html v2: address Alex comments. Signed-off-by: Dave Airlie <[email protected]> Reviewed-by: Alex Deucher <[email protected]>
* r600g: add hw register definitions for GS block setupVadim Girlin2014-02-051-0/+1
| | | | | Signed-off-by: Dave Airlie <[email protected]> Reviewed-by: Alex Deucher <[email protected]>
* r600g: implement pipeline statistics queryMarek Olšák2013-04-161-0/+3
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* r600g: emit DB_SRESULTS_COMPARE_STATE0 on r6xx/r7xxAlex Deucher2013-03-191-0/+1
| | | | | | Not using HiS yet, but matches what we do on evergreen+. Signed-off-by: Alex Deucher <[email protected]>
* r600g: flush and invalidate htile cache when appropriateMarek Olšák2013-03-011-0/+1
| | | | | | Tested-by: Andreas Boll <[email protected]> NOTE: This is a candidate for the 9.1 branch.
* r600g: add async for staging buffer upload v2Jerome Glisse2013-01-281-0/+15
| | | | | | v2: Add virtual address to dma src/dst offset for cayman Signed-off-by: Jerome Glisse <[email protected]>
* r600g: implement buffer copying using CP DMA for R7xx, Evergreen, CaymanMarek Olšák2013-01-081-0/+34
| | | | | | | | | | R6xx doesn't work - the issue seems to be with flushing (sometimes the destination buffer contains garbage). There are no hangs, so we're good. R7xx doesn't seem to have any alignment restriction despite our initial thinking. Everything just works. Reviewed-by: Alex Deucher <[email protected]>
* r600g: add htile support v16Jerome Glisse2012-12-201-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | htile is used for HiZ and HiS support and fast Z/S clears. This commit just adds the htile setup and Fast Z clear. We don't take full advantage of HiS with that patch. v2 really use fast clear, still random issue with some tiles need to try more flush combination, fix depth/stencil texture decompression v3 fix random issue on r6xx/r7xx v4 rebase on top of lastest mesa, disable CB export when clearing htile surface to avoid wasting bandwidth v5 resummarize htile surface when uploading z value. Fix z/stencil decompression, the custom blitter with custom dsa is no longer needed. v6 Reorganize render control/override update mecanism, fixing more issues in the process. v7 Add nop after depth surface base update to work around some htile flushing issue. For htile to 8x8 on r6xx/r7xx as other combination have issue. Do not enable hyperz when flushing/uncompressing depth buffer. v8 Fix htile surface, preload and prefetch setup. Only set preload and prefetch on htile surface clear like fglrx. Record depth clear value per level. Support several level for the htile surface. First depth clear can't be a fast clear. v9 Fix comments, properly account new register in emit function, disable fast zclear if clearing different layer of texture array to different value v10 Disable hyperz for texture array making test simpler. Force db_misc_state update when no depth buffer is bound. Remove unused variable, rename depth_clearstencil to depth_clear. Don't allocate htile surface for flushed depth. Something broken the cliprect change, this need to be investigated. v11 Rebase on top of newer mesa v12 Rebase on top of newer mesa v13 Rebase on top of newer mesa, htile surface need to be initialized to zero, somehow special casing first clear to not use fast clear and thus initialize the htile surface with proper value does not work in all case. v14 Use resource not texture for htile buffer make the htile buffer size computation easier and simpler. Disable preload on evergreen as its still troublesome in some case v15 Cleanup some comment and remove some left over v16 Define name for bit 20 of CP_COHER_CNTL Signed-off-by: Pierre-Eric Pelloux-Prayer <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Signed-off-by: Jerome Glisse <[email protected]>
* r600g: use SQ_VTX_SEMANTIC_CLEAR to clear the semantic registersMarek Olšák2012-10-311-0/+1
| | | | Reviewed-by: Alex Deucher <[email protected]>
* r600g: put user indices in the command stream for small index countsMarek Olšák2012-10-111-0/+1
| | | | | This improves performance a little bit if there are lots of small indexed draw commands.
* r600g: flush FMASK and CMASK when changing colorbuffers on EvergreenMarek Olšák2012-09-271-0/+1
| | | | | | This fixes rare graphical corruption. NOTE: This is a candidate for the stable branches.
* r600g: atomize framebuffer stateMarek Olšák2012-09-221-0/+1
| | | | | | Tested on RS880, Evergreen and Cayman. Reviewed-by: Alex Deucher <[email protected]>
* r600g: add support for geometry shader samplers and constant buffersMarek Olšák2012-09-131-0/+2
| | | | Reviewed-by: Jerome Glisse <[email protected]>
* r600g: simplify flushingMarek Olšák2012-09-131-0/+12
| | | | | | | | | | | | Based on the patch called "simplify and fix flushing and synchronization" by Jerome Glisse. Rebased, removed unneded code, simplified more and cleaned up. Also, SH_ACTION_ENA is not set when changing shaders (hw doesn't seem to need it). It's only used to flush constant buffers. Reviewed-by: Jerome Glisse <[email protected]>
* r600g: adjust QUANT_MODE for higher precisionVadim Girlin2012-09-041-0/+9
| | | | | | | | | Use 1/256 for R6xx/7xx, 1/4096 for evergreen, instead of default 1/16. Helps to pass some piglit tests (fbo, multisample). Signed-off-by: Vadim Girlin <[email protected]> Reviewed-by: Alex Deucher <[email protected]>
* r600g: implement MSAA for r700Marek Olšák2012-08-301-0/+20
| | | | Reviewed-by: Jerome Glisse <[email protected]>
* r600g: implement alpha-to-coverageMarek Olšák2012-08-151-0/+6
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* r600g: set DISABLE in CB_COLOR_CONTROL if colormask is 0Marek Olšák2012-07-121-0/+2
| | | | | | this will be useful for in-place DB decompression, otherwise should be harmless Reviewed-by: Alex Deucher <[email protected]>
* r600g: fix lockups with streamout on r7xxMarek Olšák2012-06-151-0/+1
| | | | | | | | | This requires the latest streamout kernel patches. Streamout is disabled by default on r7xx, so this patch is safe for regular users. Reviewed-by: Alex Deucher <[email protected]>
* r600g: initialize VS_GS_OUT_PRIM_TYPEMarek Olšák2012-03-051-0/+5
| | | | | Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Christian König <[email protected]>
* r600g: initialize SX_SURFACE_SYNCMarek Olšák2012-03-051-0/+2
| | | | | Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Christian König <[email protected]>
* r600g: rework scissor for r600-r700Marek Olšák2012-03-051-0/+2
| | | | | | | | | | | | | We must use VPORT_SCISSOR, because that's the only one we can use for multiple scissor rectangles in ARB_viewport_array. R700 can use the VPORT_SCISSOR_ENABLE bit, but R600 doesn't have that and must emit a 8192x8192 rectangle if scissor is disabled. This commit also cleanups magic numbers in create_rs_state. Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Christian König <[email protected]>
* r600g: move all invariant state from draw_vbo into start_csMarek Olšák2012-02-211-1/+0
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* r600g: turn init_config into a command buffer for starting a CSMarek Olšák2012-02-211-3/+0
| | | | | | | | | | | This is the first pure command buffer. It contains CS initialization packets and emits invariant state (i.e. the registers which never or rarely change). The affected registers are removed from *_hw_context.c, so that both ways of emitting commands can co-exist. v2: emit context_control in cayman's start_cs too
* r600g: rework cache flushingMarek Olšák2012-01-311-0/+1
| | | | | | | | | | | This also significantly improves the RV670 flush by using the CB1 flush *always* and also DEST_BASE_0_ENA, which appears to magically fix some tests. I am not entirely sure, but it's possible that RV670 flushing is fixed completely. v2: fix cayman by flushing texture cache instead of vertex cache Thanks to Dave Airlie for testing Cayman.
* r600g: clean up register headersAlex Deucher2012-01-231-1/+0
| | | | | | | | - CP_INTERRUPT packet doesn't exist - remove lots of r6xx copy/paste remnants from evergreen reg header - fix some cayman specific registers Signed-off-by: Alex Deucher <[email protected]>
* r600g: implement clip vertex v2Vadim Girlin2012-01-211-0/+4
| | | | | | | | Clip planes are uploaded as a constant buffer and used by the vertex shader to produce corresponding clip distances for hw clipping. Signed-off-by: Vadim Girlin <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* r600g: implement transform feedbackMarek Olšák2011-12-171-0/+51
| | | | | | | | r600: DONE. r700: MOSTLY (done but locks up). Evergreen: MOSTLY (done but doesn't work for an unknown reason). The kernel support will come soon.
* r600g: fix the representation of control-flow instructionsMarek Olšák2011-11-151-34/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | We need something that looks like a compiler and not like some hacker put some functions together. /rant This is a band-aid for these two problems: - The R600 and EG control-flow instructions appear in switch statements next to each other, causing conflicts when adding new instructions. - The ALU control-flow instructions are bitshifted by 3 (from CF_INST 26:29 to CF_INST 23:29, as is defined by r600 ISA) even for EG, where CF_INST is 22:29. To fix this mess, the 'inst' field is bitshifted to the left either by 22, 23, or 26 (directly in the definitions), such that it can be just or'd when making bytecode without any shifting. All switch statements have been divided into two, one for R600 and the other for EG. Of course, there is a better way to do this, but that is left for future work. Tested on RV730 and REDWOOD with no regressions. v2: minor cleanup as per Alex's comment. Reviewed-by: Alex Deucher <[email protected]>
* r600g: add initial linestipple support.Dave Airlie2011-11-061-0/+5
| | | | | | | It seems line loop stipple in hardware needs something I don't know, it might need a proper geometry shader who knows. Signed-off-by: Dave Airlie <[email protected]>
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