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path: root/src/gallium/drivers/r600/r600d.h
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* r600g: implement alpha-to-coverageMarek Olšák2012-08-151-0/+6
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* r600g: set DISABLE in CB_COLOR_CONTROL if colormask is 0Marek Olšák2012-07-121-0/+2
| | | | | | this will be useful for in-place DB decompression, otherwise should be harmless Reviewed-by: Alex Deucher <[email protected]>
* r600g: fix lockups with streamout on r7xxMarek Olšák2012-06-151-0/+1
| | | | | | | | | This requires the latest streamout kernel patches. Streamout is disabled by default on r7xx, so this patch is safe for regular users. Reviewed-by: Alex Deucher <[email protected]>
* r600g: initialize VS_GS_OUT_PRIM_TYPEMarek Olšák2012-03-051-0/+5
| | | | | Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Christian König <[email protected]>
* r600g: initialize SX_SURFACE_SYNCMarek Olšák2012-03-051-0/+2
| | | | | Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Christian König <[email protected]>
* r600g: rework scissor for r600-r700Marek Olšák2012-03-051-0/+2
| | | | | | | | | | | | | We must use VPORT_SCISSOR, because that's the only one we can use for multiple scissor rectangles in ARB_viewport_array. R700 can use the VPORT_SCISSOR_ENABLE bit, but R600 doesn't have that and must emit a 8192x8192 rectangle if scissor is disabled. This commit also cleanups magic numbers in create_rs_state. Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Christian König <[email protected]>
* r600g: move all invariant state from draw_vbo into start_csMarek Olšák2012-02-211-1/+0
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* r600g: turn init_config into a command buffer for starting a CSMarek Olšák2012-02-211-3/+0
| | | | | | | | | | | This is the first pure command buffer. It contains CS initialization packets and emits invariant state (i.e. the registers which never or rarely change). The affected registers are removed from *_hw_context.c, so that both ways of emitting commands can co-exist. v2: emit context_control in cayman's start_cs too
* r600g: rework cache flushingMarek Olšák2012-01-311-0/+1
| | | | | | | | | | | This also significantly improves the RV670 flush by using the CB1 flush *always* and also DEST_BASE_0_ENA, which appears to magically fix some tests. I am not entirely sure, but it's possible that RV670 flushing is fixed completely. v2: fix cayman by flushing texture cache instead of vertex cache Thanks to Dave Airlie for testing Cayman.
* r600g: clean up register headersAlex Deucher2012-01-231-1/+0
| | | | | | | | - CP_INTERRUPT packet doesn't exist - remove lots of r6xx copy/paste remnants from evergreen reg header - fix some cayman specific registers Signed-off-by: Alex Deucher <[email protected]>
* r600g: implement clip vertex v2Vadim Girlin2012-01-211-0/+4
| | | | | | | | Clip planes are uploaded as a constant buffer and used by the vertex shader to produce corresponding clip distances for hw clipping. Signed-off-by: Vadim Girlin <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* r600g: implement transform feedbackMarek Olšák2011-12-171-0/+51
| | | | | | | | r600: DONE. r700: MOSTLY (done but locks up). Evergreen: MOSTLY (done but doesn't work for an unknown reason). The kernel support will come soon.
* r600g: fix the representation of control-flow instructionsMarek Olšák2011-11-151-34/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | We need something that looks like a compiler and not like some hacker put some functions together. /rant This is a band-aid for these two problems: - The R600 and EG control-flow instructions appear in switch statements next to each other, causing conflicts when adding new instructions. - The ALU control-flow instructions are bitshifted by 3 (from CF_INST 26:29 to CF_INST 23:29, as is defined by r600 ISA) even for EG, where CF_INST is 22:29. To fix this mess, the 'inst' field is bitshifted to the left either by 22, 23, or 26 (directly in the definitions), such that it can be just or'd when making bytecode without any shifting. All switch statements have been divided into two, one for R600 and the other for EG. Of course, there is a better way to do this, but that is left for future work. Tested on RV730 and REDWOOD with no regressions. v2: minor cleanup as per Alex's comment. Reviewed-by: Alex Deucher <[email protected]>
* r600g: add initial linestipple support.Dave Airlie2011-11-061-0/+5
| | | | | | | It seems line loop stipple in hardware needs something I don't know, it might need a proper geometry shader who knows. Signed-off-by: Dave Airlie <[email protected]>
* r600g: cleanup some magic numbersMarek Olšák2011-10-251-0/+6
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* r600g: add support for shadow array samplersMarek Olšák2011-09-101-12/+28
| | | | I had to guess & verify how some of the SAMPLE instructions work.
* r600g: add TXQ and TXF supportDave Airlie2011-09-061-0/+1
| | | | Signed-off-by: Dave Airlie <[email protected]>
* r600g: consolidate two files r600d.hMarek Olšák2011-08-161-1/+55
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* r600g: remove some magic numbersMarek Olšák2011-06-191-0/+3
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* r600g: fix TXD when shadowing is enabled.Mike Kaplinskiy2011-06-151-3/+4
| | | | | | | | Mike had actually done a lot of the TXD support in a patch in bug 37476 which I see now, I'll add the bits of his work that I didn't think to add to my work. Signed-off-by: Dave Airlie <[email protected]>
* r600g: add TXD support.Dave Airlie2011-06-151-0/+4
| | | | | | | | This at least passes the piglit arb_shader_texture_lod-texgrad test, the AMD shader analyzer seems to multiply the V component by an unspecified constant value no idea why. Signed-off-by: Dave Airlie <[email protected]>
* r600g: anisotropic filtering support for evergreen hwJerome Glisse2011-05-091-6/+6
| | | | Signed-off-by: Jerome Glisse <[email protected]>
* r600g: add support for anisotropic filteringCarl-Philip Haensch2011-05-091-0/+9
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* r600g: Cleanup the big endian support a bit.Henri Verbeet2011-04-251-5/+0
| | | | | | | In particular, make sure the code is at least compiled on little endian systems. Signed-off-by: Henri Verbeet <[email protected]>
* r600g: add big endian support for r6xx/r7xxCédric Cano2011-04-191-0/+6
| | | | | Signed-off-by: Cedric Cano <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* r600g: add NV_conditional_render support.Dave Airlie2011-03-011-0/+4
| | | | | | | | This is reliant on a drm patch that I posted on the list + a version bump. These will appear in drm-next today. Signed-off-by: Dave Airlie <[email protected]>
* r600g: handle 16/32 u/s norm formats properlyDave Airlie2011-02-111-0/+2
| | | | | | | add support for the 32-bit types, also fixup the export setting to handle types with channels > 11 bits properly Signed-off-by: Dave Airlie <[email protected]>
* r600g: handle the write all cbufs property.Dave Airlie2011-01-311-25/+0
| | | | | | | | | | This only works on r600/r700 so far, evergreen doesn't appear to have the multiwrite enable bit in the color control, so we may have to actually do a shader rewrite on EG hardware. remove some duplicate code reg defines also. Signed-off-by: Dave Airlie <[email protected]>
* r600g: Fix some register value name typos.Henri Verbeet2011-01-151-2/+2
| | | | SFR -> SRF.
* r600g: set hardware pixel centers according to gl_rasterization_rulesKeith Whitwell2010-11-031-0/+4
| | | | | | | These were previously being left in the default (D3D) mode. This mean that triangles were drawn slightly incorrectly, but also because this state is relied on by the u_blitter code, all blits were half a pixel off.
* r600g: add defines for tilingDave Airlie2010-10-181-0/+4
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* r600g: switch to a common formats.h file since they are in different regsDave Airlie2010-10-181-39/+1
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* r600g: add shader stencil export support.Dave Airlie2010-10-131-0/+3
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* r600g: setup basic loop consts on r600 + evergreen.Dave Airlie2010-10-011-0/+2
| | | | this sets up a single loop constant like r600c does.
* r600g: fixup vertex format picking.Dave Airlie2010-10-011-34/+39
| | | | there are some vertex formats defined in r600c not in the docs.
* r600g: add winsys support for CTL constants.Dave Airlie2010-10-011-0/+3
| | | | | These need to be emitted, we also need them to do proper vtx start, instead of abusing index offset.
* r600g: use constant buffer instead of register for constantJerome Glisse2010-09-301-0/+5
| | | | Signed-off-by: Jerome Glisse <[email protected]>
* r600g: add some more vertex format support.Dave Airlie2010-09-241-0/+3
| | | | adds the sscaled formats, this passes some more of the draw-vertices tests.
* r600g: cleanup some of the DB blit codeDave Airlie2010-09-221-0/+7
| | | | | | | | | add cb/db flush states to the blit code. add support for the rv6xx that need special treatment. according to R6xx_7xx_3D.pdf set r700 CB_SHADER_CONTROL reg in blit code docs say dual export should be disabled for DB->CB
* r600g: Clean up PS setup.Corbin Simpson2010-09-191-0/+6
| | | | | I didn't do r600d according to the docs; I split EXPORT_MODE to be a bit more useful and obvious. Hope this is okay.
* r600g: Deobfuscate and comment a few more functions in r600_hw_states.Corbin Simpson2010-09-191-0/+33
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* r600g: alternative command stream building from contextJerome Glisse2010-09-171-7/+2099
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Winsys context build a list of register block a register block is a set of consecutive register that will be emited together in the same pm4 packet (the various r600_block* are there to provide basic grouping that try to take advantage of states that are linked together) Some consecutive register are emited each in a different block, for instance the various cb[0-7]_base. At winsys context creation, the list of block is created & an index into the list of block. So to find into which block a register is in you simply use the register offset and lookup the block index. Block are grouped together into group which are the various pkt3 group of config, context, resource, Pipe state build a list of register each state want to modify, beside register value it also give a register mask so only subpart of a register can be updated by a given pipe state (the oring is in the winsys) There is no prebuild register list or define for each pipe state. Once pipe state are built they are bound to the winsys context. Each of this functions will go through the list of register and will find into which block each reg falls and will update the value of the block with proper masking (vs/ps resource/constant are specialized variant with somewhat limited capabilities). Each block modified by r600_context_pipe_state_set* is marked as dirty and we update a count of dwords needed to emit all dirty state so far. r600_context_pipe_state_set* should be call only when pipe context change some of the state (thus when pipe bind state or set state) Then to draw primitive you make a call to r600_context_draw void r600_context_draw(struct r600_context *ctx, struct r600_draw *draw) It will check if there is enough dwords in current cs buffer and if not will flush. Once there is enough room it will copy packet from dirty block and then add the draw packet3 to initiate the draw. The flush will send the current cs, reset the count of dwords to 0 and remark all states that are enabled as dirty and recompute the number of dwords needed to send the current context. Signed-off-by: Jerome Glisse <[email protected]>
* r600g: Fixed the shift in S_02880C_KILL_ENABLE.Tilman Sauerbeck2010-09-171-1/+1
| | | | Signed-off-by: Tilman Sauerbeck <[email protected]>
* r600g: Added DB_SHADER_CONTROL defines.Tilman Sauerbeck2010-09-171-0/+17
| | | | Signed-off-by: Tilman Sauerbeck <[email protected]>
* r600g: add vgt dma src definesDave Airlie2010-09-161-0/+2
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* r600g: drop magic numbers in depth state.Dave Airlie2010-09-031-0/+7
| | | | this also fixes occulsion queries.
* r600g: add missing vertex fetch formats to the translation table.Dave Airlie2010-09-021-0/+1
| | | | fixes at least 2 more piglits.
* r600g: fix TXP vs TEX in shader.Dave Airlie2010-08-181-0/+7
| | | | | | Don't do perspective for TEX, and also copy input to a temporary for TEX also add tex opcode names
* r600g: add point/sprite rendering supportJerome Glisse2010-08-111-0/+80
| | | | Signed-off-by: Jerome Glisse <[email protected]>
* r600g: add PA_CL_CLIP_CNTL definitionJerome Glisse2010-08-061-0/+55
| | | | Signed-off-by: Jerome Glisse <[email protected]>
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