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path: root/src/gallium/drivers/r600/r600d.h
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* r600g: add NV_conditional_render support.Dave Airlie2011-03-011-0/+4
| | | | | | | | This is reliant on a drm patch that I posted on the list + a version bump. These will appear in drm-next today. Signed-off-by: Dave Airlie <[email protected]>
* r600g: handle 16/32 u/s norm formats properlyDave Airlie2011-02-111-0/+2
| | | | | | | add support for the 32-bit types, also fixup the export setting to handle types with channels > 11 bits properly Signed-off-by: Dave Airlie <[email protected]>
* r600g: handle the write all cbufs property.Dave Airlie2011-01-311-25/+0
| | | | | | | | | | This only works on r600/r700 so far, evergreen doesn't appear to have the multiwrite enable bit in the color control, so we may have to actually do a shader rewrite on EG hardware. remove some duplicate code reg defines also. Signed-off-by: Dave Airlie <[email protected]>
* r600g: Fix some register value name typos.Henri Verbeet2011-01-151-2/+2
| | | | SFR -> SRF.
* r600g: set hardware pixel centers according to gl_rasterization_rulesKeith Whitwell2010-11-031-0/+4
| | | | | | | These were previously being left in the default (D3D) mode. This mean that triangles were drawn slightly incorrectly, but also because this state is relied on by the u_blitter code, all blits were half a pixel off.
* r600g: add defines for tilingDave Airlie2010-10-181-0/+4
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* r600g: switch to a common formats.h file since they are in different regsDave Airlie2010-10-181-39/+1
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* r600g: add shader stencil export support.Dave Airlie2010-10-131-0/+3
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* r600g: setup basic loop consts on r600 + evergreen.Dave Airlie2010-10-011-0/+2
| | | | this sets up a single loop constant like r600c does.
* r600g: fixup vertex format picking.Dave Airlie2010-10-011-34/+39
| | | | there are some vertex formats defined in r600c not in the docs.
* r600g: add winsys support for CTL constants.Dave Airlie2010-10-011-0/+3
| | | | | These need to be emitted, we also need them to do proper vtx start, instead of abusing index offset.
* r600g: use constant buffer instead of register for constantJerome Glisse2010-09-301-0/+5
| | | | Signed-off-by: Jerome Glisse <[email protected]>
* r600g: add some more vertex format support.Dave Airlie2010-09-241-0/+3
| | | | adds the sscaled formats, this passes some more of the draw-vertices tests.
* r600g: cleanup some of the DB blit codeDave Airlie2010-09-221-0/+7
| | | | | | | | | add cb/db flush states to the blit code. add support for the rv6xx that need special treatment. according to R6xx_7xx_3D.pdf set r700 CB_SHADER_CONTROL reg in blit code docs say dual export should be disabled for DB->CB
* r600g: Clean up PS setup.Corbin Simpson2010-09-191-0/+6
| | | | | I didn't do r600d according to the docs; I split EXPORT_MODE to be a bit more useful and obvious. Hope this is okay.
* r600g: Deobfuscate and comment a few more functions in r600_hw_states.Corbin Simpson2010-09-191-0/+33
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* r600g: alternative command stream building from contextJerome Glisse2010-09-171-7/+2099
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Winsys context build a list of register block a register block is a set of consecutive register that will be emited together in the same pm4 packet (the various r600_block* are there to provide basic grouping that try to take advantage of states that are linked together) Some consecutive register are emited each in a different block, for instance the various cb[0-7]_base. At winsys context creation, the list of block is created & an index into the list of block. So to find into which block a register is in you simply use the register offset and lookup the block index. Block are grouped together into group which are the various pkt3 group of config, context, resource, Pipe state build a list of register each state want to modify, beside register value it also give a register mask so only subpart of a register can be updated by a given pipe state (the oring is in the winsys) There is no prebuild register list or define for each pipe state. Once pipe state are built they are bound to the winsys context. Each of this functions will go through the list of register and will find into which block each reg falls and will update the value of the block with proper masking (vs/ps resource/constant are specialized variant with somewhat limited capabilities). Each block modified by r600_context_pipe_state_set* is marked as dirty and we update a count of dwords needed to emit all dirty state so far. r600_context_pipe_state_set* should be call only when pipe context change some of the state (thus when pipe bind state or set state) Then to draw primitive you make a call to r600_context_draw void r600_context_draw(struct r600_context *ctx, struct r600_draw *draw) It will check if there is enough dwords in current cs buffer and if not will flush. Once there is enough room it will copy packet from dirty block and then add the draw packet3 to initiate the draw. The flush will send the current cs, reset the count of dwords to 0 and remark all states that are enabled as dirty and recompute the number of dwords needed to send the current context. Signed-off-by: Jerome Glisse <[email protected]>
* r600g: Fixed the shift in S_02880C_KILL_ENABLE.Tilman Sauerbeck2010-09-171-1/+1
| | | | Signed-off-by: Tilman Sauerbeck <[email protected]>
* r600g: Added DB_SHADER_CONTROL defines.Tilman Sauerbeck2010-09-171-0/+17
| | | | Signed-off-by: Tilman Sauerbeck <[email protected]>
* r600g: add vgt dma src definesDave Airlie2010-09-161-0/+2
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* r600g: drop magic numbers in depth state.Dave Airlie2010-09-031-0/+7
| | | | this also fixes occulsion queries.
* r600g: add missing vertex fetch formats to the translation table.Dave Airlie2010-09-021-0/+1
| | | | fixes at least 2 more piglits.
* r600g: fix TXP vs TEX in shader.Dave Airlie2010-08-181-0/+7
| | | | | | Don't do perspective for TEX, and also copy input to a temporary for TEX also add tex opcode names
* r600g: add point/sprite rendering supportJerome Glisse2010-08-111-0/+80
| | | | Signed-off-by: Jerome Glisse <[email protected]>
* r600g: add PA_CL_CLIP_CNTL definitionJerome Glisse2010-08-061-0/+55
| | | | Signed-off-by: Jerome Glisse <[email protected]>
* r600g: fix color format, indentation, definesJerome Glisse2010-08-061-7/+12
| | | | Signed-off-by: Jerome Glisse <[email protected]>
* r600g: add SRGB support.Dave Airlie2010-08-061-0/+2
| | | | This enables GL2.1 and passes glean's texture_srgb test.
* r600g: improve supported format selection.Dave Airlie2010-08-061-0/+5
| | | | | | | This fixes fbo-readpixels piglit test, and adds support for swapping the formats. Not all formats are correct yet I don't think. Signed-off-by: Dave Airlie <[email protected]>
* r600g: always perform texture perspective divide + fix blendingJerome Glisse2010-08-041-0/+25
| | | | | | quake3 engine seems to run fine at this point (ioquake) Signed-off-by: Jerome Glisse <[email protected]>
* r600g: add polygon offset supportJerome Glisse2010-08-031-0/+23
| | | | Signed-off-by: Jerome Glisse <[email protected]>
* r600g: add autogenerated reg definition + debug print cleanupJerome Glisse2010-08-021-0/+97
| | | | Signed-off-by: Jerome Glisse <[email protected]>
* r600g: mipmap early support + EX2/ABS instruction + cullingJerome Glisse2010-07-291-0/+40
| | | | | | | | | | Add mipmap support (demos/src/redbook/mipmap is working) Add EX2/ABS shader instruction support. Add face culling support. Misc fixes. Signed-off-by: Jerome Glisse <[email protected]>
* r600g: texture supportJerome Glisse2010-07-271-0/+235
| | | | | | | | | | | | | Add texture mapping support, redbook/texbind works if you comment out glClear and second checkboard. Need to fix : - texture overwritting - lod & mip/map handling - unormalized coordinate handling - texture view with first leve > 0 - and many other things Signed-off-by: Jerome Glisse <[email protected]>
* r600g: add support for all R6XX/R7XX asicJerome Glisse2010-07-211-0/+75
| | | | | | | This configure some of the value properly based on asic so others asic than RV710 works too. Signed-off-by: Jerome Glisse <[email protected]>
* r600g: Initial importJerome Glisse2010-05-271-0/+677