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* gallium: switch boolean -> bool at the interface definitionsIlia Mirkin2019-07-221-11/+11
| | | | | | | | | | | | | | | | | | This is a relatively minimal change to adjust all the gallium interfaces to use bool instead of boolean. I tried to avoid making unrelated changes inside of drivers to flip boolean -> bool to reduce the risk of regressions (the compiler will much more easily allow "dirty" values inside a char-based boolean than a C99 _Bool). This has been build-tested on amd64 with: Gallium drivers: nouveau r300 r600 radeonsi freedreno swrast etnaviv v3d vc4 i915 svga virgl swr panfrost iris lima kmsro Gallium st: mesa xa xvmc xvmc vdpau va Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Acked-by: Alyssa Rosenzweig <[email protected]>
* r600: reset tex array override even when no view boundDave Airlie2019-05-021-11/+10
| | | | | | | | | | If no view is bound we still should reset the override to 0 and array mode. This should fix misrendering in firefox WebRender since the pbo sampler was removed. Fixes: 1250383e36 (st/mesa: remove sampler associated with buffer texture in pbo logic)
* gallium: enable GL_AMD_depth_clamp_separate on r600, radeonsiMarek Olšák2018-09-061-1/+1
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* gallium: split depth_clip into depth_clip_near & depth_clip_farMarek Olšák2018-09-061-2/+2
| | | | for AMD_depth_clamp_separate.
* gallium: add storage_sample_count parameter into is_format_supportedMarek Olšák2018-07-311-0/+4
| | | | Tested-by: Dieter Nützel <[email protected]>
* r600g: constify some variablesKonstantin Kharlamov2018-07-171-6/+6
| | | | | | | Just a nice hint for both peoples and compilers. Signed-off-by: Konstantin Kharlamov <[email protected]> Signed-off-by: Marek Olšák <[email protected]>
* r600: fix build after the removal of RADEON_PRIO_* flagsMarek Olšák2018-07-161-4/+2
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* radeonsi: merge DCC/CMASK/HTILE priority flagsMarek Olšák2018-07-161-1/+1
| | | | | | For a later simplification. Reviewed-by: Samuel Pitoiset <[email protected]>
* gallium/util: remove dummy function util_format_is_supportedMarek Olšák2018-06-291-3/+0
| | | | Reviewed-by: Eric Engestrom <[email protected]>
* amd,radeonsi: rename radeon_winsys_cs -> radeon_cmdbufMarek Olšák2018-06-191-17/+17
| | | | Acked-by: Bas Nieuwenhuizen <[email protected]>
* r600: fix constant buffer bounds.Dave Airlie2018-05-101-1/+1
| | | | | | | | | | | | | | | | | | | | If you have an indirect access to a constant buffer on r600/eg use a vertex fetch in the shader. However apps have expected behaviour on those out of bounds accessess (even if illegal). If the constants were being uploaded as part of a larger upload buffer, we'd set the range of allowed access to a lot larger than required so apps would get values back from other parts of the upload buffer instead of the expected out of bounds access. This fixes rendering bugs in Trine and Witcher 1, thanks to iive for nagging me effectively until I figured it out :-) Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91808 Cc: <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]>
* r600: fix color export maskRoland Scheidegger2018-03-051-0/+1
| | | | | | | | | | | The r600 code (not the eg one) forgot to copy the ps_color_export_mask in commit 5b14e06d8b42e2b08ebc52b6c314ef8647d87a1f when updating the pixel state, leading to misrenderings (probably with MRT). Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105262 Tested-by: LoneVVolf <[email protected]> Tested-by: Pavel Vinogradov <[email protected]>
* r600: fix rendering regression on r6/7 gpusDave Airlie2018-02-081-1/+6
| | | | | | | | Fixes: 2d5b5d267e (r600: work out target mask at framebuffer bind.) Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104989 Reviewed-by: Roland Scheidegger <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* r600: work out target mask at framebuffer bind.Dave Airlie2018-02-071-1/+1
| | | | | | | If we only get 1,2,3,6 framebuffers we want a sparse target mask. Reviewed-by: Roland Scheidegger <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* r600: work out shader export mask at shader build time (v1.1)Dave Airlie2018-02-071-1/+1
| | | | | | | | | | | Since enhanced layouts allows setting specific MRT outputs, we can get sparse outputs, so we have to calculate the shader mask earlier. v1.1: update checks for state update (Roland) Reviewed-by: Roland Scheidegger <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* r600: increase number of ubos by one to 14Roland Scheidegger2018-01-101-0/+1
| | | | | | | | | | | | | | | Ideally we'd support 16 (d3d11 requires 15, and mesa subtracts one for non-ubo constants), but that's kind of impossible (it would be only doable if either we'd somehow merge the mesa non-ubo constants with the driver constants, or only use the driver constants with vtx fetch instead of through the kcache mechanism - the latter probably wouldn't be too bad). For now just do as the comment already said, place the gs ring (not really a const buffer in any case) which is only ever referred to through vc fetch clauses at index 16. Throw in a couple asserts for good measure to make sure the hw limit isn't exceeded. Tested-by: Konstantin Kharlamov <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* r600: don't emit reloc for ring buffer out into the blueRoland Scheidegger2018-01-101-4/+3
| | | | | | | It looks like this reloc belongs to setting the constant reg, which is skipped for gs ring. Reviewed-by: Dave Airlie <[email protected]>
* ac: change legacy_surf_level::slice_size to dword unitsMarek Olšák2017-11-271-4/+4
| | | | | | | | | The next commit will reduce the size even more. v2: typecast to uint64_t manually v3: add more typecasts, add asserts Reviewed-by: Nicolai Hähnle <[email protected]>
* r600: set the number type correctly for float rts in cb setupRoland Scheidegger2017-11-151-1/+9
| | | | | | | | | | | | Float rts were always set as unorm instead of float. Not sure of the consequences, but at least it looks like the blend clamp would have been enabled, which is against the rules (only eg really bothered to even attempt to specify this correctly, r600 always used clamp anyway). Albeit r600 (not r700) setup still looks bugged to me due to never setting BLEND_FLOAT32 which must be set according to docs... Not sure if the hw really cares, no piglit change (on eg/juniper). Reviewed-by: Dave Airlie <[email protected]>
* r600: use DX10_CLAMP bit in shader setupRoland Scheidegger2017-11-151-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The docs are not very concise in what this really does, however both Alex Deucher and Nicolai Hähnle suggested this only really affects instructions using the CLAMP output modifier, and I've confirmed that with the newly changed piglit isinf_and_isnan test. So, with this bit set, if an instruction has the CLAMP modifier bit (which clamps to [0,1]) set, then NaNs will be converted to zero, otherwise the result will be NaN. D3D10 would require this, glsl doesn't have modifiers (with mesa clamp(x,0,1) would get converted to such a modifier) coupled with a whatever-floats-your-boat specified NaN behavior, but the clamp behavior should probably always be used (this also matches what a decomposition into min(1.0, max(x, 0.0)) would do, if min/max also adhere to the ieee spec of picking the non-nan result). Some apps may in fact rely on this, as this prevents misrenderings in This War of Mine since using ieee muls (ce7a045feeef8cad155f1c9aa07f166e146e3d00), without having to use clamped rcp opcode, which would also fix this bug there. radeonsi also seems to set this bit nowadays if I see that righ (albeit the llvm amdgpu code comment now says "Make clamp modifier on NaN input returns 0" instead of "Do not clamp NAN to 0" since it was changed, which also looks a bit misleading). v2: set it in all shader stages. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103544 Reviewed-by: Dave Airlie <[email protected]>
* r600g: use SIMPLE_FLOAT for blending to enable some optimizationsIlia Mirkin2017-11-081-0/+1
| | | | | | | | | | | Radeonsi also sets this flag. Seems to avoid pulling up the desintation RT value when the dst blend factor is zero if it's not otherwise being loaded. Among other things, it allows blending to overwrite infinity/NaN values in the destination RT. Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/radeon: add helpers for whether HTILE is enabledMarek Olšák2017-08-221-2/+1
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* r600g: don't set up and don't call the fetch shader if there are no VS inputsMarek Olšák2017-08-211-0/+3
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* gallium/radeon: don't allocate HTILE in a separate bufferMarek Olšák2017-06-081-3/+3
| | | | | Reviewed-by: Samuel Pitoiset <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium: decrease the size of pipe_vertex_buffer - 24 -> 16 bytesMarek Olšák2017-05-101-1/+1
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* r600g: update dirty_level_mask after the 1-st draw after FB changeConstantine Kharlamov2017-04-191-0/+1
| | | | | | | | | | | Ported from radeonsi. Testing with Kane&Lynch2 shows ≈1k skipped updates per frame on average. No piglit changes with tests/gpu.py, gbm mode. Signed-off-by: Constantine Kharlamov <[email protected]> Tested-by: Dieter Nützel <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* r600g: add draw_vbo check for a NULL pixel shaderConstantine Kharlamov2017-04-101-1/+2
| | | | | | | | Taken from radeonsi, required to remove dummy pixel shader in the next patch Signed-off-by: Constantine Kharlamov <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Signed-off-by: Marek Olšák <[email protected]>
* gallium/radeon: move pre-GFX9 radeon_surf.* members to radeon_surf.u.legacy.*Marek Olšák2017-03-301-32/+32
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* r600g: check NULL return from r600_aligned_buffer_createJulien Isorce2017-03-281-0/+10
| | | | | Signed-off-by: Julien Isorce <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* r600g: make framebuffer atom rely on dual src blend state.Dave Airlie2017-03-151-1/+1
| | | | | | | | In order to make ARB_shader_image_load_store, we have to share the CB space with RATs, so we should only steal the dual src space if we have dual src enabled. Signed-off-by: Dave Airlie <[email protected]>
* gallium/radeon: prevent SDMA stalls by detecting RAW hazards in need_dma_spaceMarek Olšák2017-01-051-1/+0
| | | | | | | | Call r600_dma_emit_wait_idle only when there is a possibility of a read-after-write hazard. Buffers not yet used by the SDMA IB don't have to wait. Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/radeon: remove radeon_surf_level::pitch_bytesMarek Olšák2016-11-011-2/+2
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* r600g: remove a redundant buffer_create helperMarek Olšák2016-10-261-23/+8
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/radeon: don't do (fmask.size && cmask.size)Marek Olšák2016-10-261-1/+1
| | | | | | fmask implies that cmask is present too. Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/radeon: remove unnecessary fields from radeon_surf_levelMarek Olšák2016-10-261-4/+4
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/radeon: stop using some input fields from radeon_surfaceMarek Olšák2016-10-261-1/+1
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium: remove PIPE_BIND_TRANSFER_READ/WRITEMarek Olšák2016-09-081-5/+0
| | | | | | | | not used in any useful way Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]>
* gallium/radeon: remove VPORT_ZMIN/ZMAX from init config statesMarek Olšák2016-09-051-6/+0
| | | | | | | It's part of the viewport state now. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/radeon: set VPORT_ZMIN/MAX registers correctlyMarek Olšák2016-09-051-0/+1
| | | | | | | | | | | | Calculate depth ranges from viewport states and pipe_rasterizer_state::clip_halfz. The evergreend.h change is required to silence a warning. This fixes this recently updated piglit: arb_depth_clamp/depth-clamp-range Reviewed-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/radeon: merge USER_SHADER and INTERNAL_SHADER priority flagsMarek Olšák2016-08-261-1/+1
| | | | | | there's no reason to separate these Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* gallium: change pipe_sampler_view::first_element/last_element -> offset/sizeMarek Olšák2016-08-171-2/+2
| | | | | | | | | | | This is required by OpenGL. Our hardware supports this. Example: Bind RGBA32F with offset = 4 bytes. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=97305 Acked-by: Ilia Mirkin <[email protected]> Acked-by: Nicolai Hähnle <[email protected]>
* gallium/radeon: mark shader rings as highest-priority buffersMarek Olšák2016-08-171-2/+2
| | | | | | | and rename the enum Acked-by: Edward O'Callaghan <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/radeon: replace is_flushing_texture with db_compatibleNicolai Hähnle2016-07-061-3/+3
| | | | | | | | | | | This is a left-over of when I considered generalizing the separate stencil support. I do prefer the new name since it emphasizes what flushing vs. non-flushing means from a functional point-of-view, namely special handling of the texture format. v2: adjust r600_init_color_surface as well Reviewed-by: Marek Olšák <[email protected]>
* gallium/radeon: add can_sample_z/s flags for texturesNicolai Hähnle2016-07-061-8/+8
| | | | | | v2: adjust r600_init_color_surface as well Reviewed-by: Marek Olšák <[email protected]>
* gallium/radeon: use r600_resource_referenceMarek Olšák2016-06-251-10/+6
| | | | | | Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Vedran Miletić <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* r600g: Implement POLYGON_OFFSET_UNITS_UNSCALEDAxel Davy2016-06-251-16/+19
| | | | | | | | | | | | | | | | Empirical tests show that the polygon offset behaviour is entirely determined by the content of the PA_SU_POLY_OFFSET states, and not by the depth buffer format bound. PA_SU_POLY_OFFSET seems to directly set the parameters of the polygon offset formula, and setting 0 for PA_SU_POLY_OFFSET_DB_FMT_CNTL (ie setting the unorm depth bias behaviour with a scale of 2^0 = 1.0f) gives the unscaled behaviour. Signed-off-by: Axel Davy <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* r600g: move PA_SU_POLY_OFFSET_DB_FMT_CNTL to poly offset states for r600Axel Davy2016-06-251-24/+13
| | | | | | | | | | | Emit PA_SU_POLY_OFFSET_DB_FMT_CNTL with the other poly_offset states. This will be useful to implement PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED. v2: Increase the num_dw field for the poly offset atom Signed-off-by: Axel Davy <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* gallium/radeon: disable complicated point clipping against user clip planesMarek Olšák2016-06-241-1/+0
| | | | | | Nothing in the GL spec says that we should expand points to triangles. Reviewed-by: Nicolai Hähnle <[email protected]>
* r600g: don't flush caches when binding shader resourcesMarek Olšák2016-06-041-14/+11
| | | | | | Reviewed-by: Alex Deucher <[email protected]> Tested-by: Grazvydas Ignotas <[email protected]> Tested-by: Dieter Nützel <[email protected]>
* r600: Change default behaviour for undefined COLOR0Axel Davy2016-05-181-0/+4
| | | | | | | | | d3d 9 needs COLOR0 to be 1.0 on all channels when undefined. 0.0 for the others is fine. GL behaviour is undefined. Signed-off-by: Axel Davy <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
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