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path: root/src/gallium/drivers/r600/r600_shader.c
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* radeon/winsys: move radeon family/class identification to winsysJerome Glisse2013-01-071-0/+1
* r600g: refactor and make streamout dumping more informativeMarek Olšák2012-12-201-12/+21
* r600g: try to fix streamout for the cases where BURST_COUNT > 0Marek Olšák2012-12-201-1/+1
* r600g: lower stream outputs with dst_offset < start_componentMarek Olšák2012-12-201-7/+47
* r600g: use r600_get_temp to get temporaries for CLIPDIST shader outputsMarek Olšák2012-12-201-3/+11
* r600g: initialize inst_mod in r600_tex_from_byte_streamVadim Girlin2012-12-181-0/+2
* r600g: fixup offset types for printingDave Airlie2012-12-161-1/+1
* r600g/radeonsi: Silence warningsMaxence Le Dore2012-12-131-2/+3
* r600g: use load_ar checks with llvm output.Vincent Lejeune2012-12-131-0/+6
* r600g: mirror simplification of if/break opcodesVincent Lejeune2012-11-291-32/+12
* r600g: add initial cube map array support (v2)Dave Airlie2012-11-101-11/+187
* r600g: fix lod bias/explicit lod with cube maps.Dave Airlie2012-11-091-8/+20
* r600g: clarify const buffer numbering and handlingDave Airlie2012-11-091-1/+1
* r600g/compute: fix call to r600_bytecode_initAlex Deucher2012-11-071-1/+2
* r600g: make tgsi-to-llvm generates store.pixel* intrinsic for fsVincent Lejeune2012-11-021-4/+28
* r600g: tgsi-to-llvm emits right input intrinsicsVincent Lejeune2012-10-301-7/+15
* r600g: implement texturing with 8x MSAA compressed surfaces for EvergreenMarek Olšák2012-10-291-3/+130
* r600g: rewrite tgsi-to-llvm load-input to handle fragcoordVincent Lejeune2012-10-241-1/+1
* r600g: Remove special handling of PRED_SET* insructions for LLVM 3.2Tom Stellard2012-10-191-0/+2
* r600g: move shader structures into r600_shader.hMarek Olšák2012-10-121-0/+1
* r600g: remove the dual_src_blend flag from the shader keyMarek Olšák2012-10-101-1/+1
* r600g: use a select to handle front/back color in llvmVincent Lejeune2012-10-091-5/+8
* r600g: frontcolor tracks its associated backcolorVincent Lejeune2012-10-091-25/+34
* r600g: add some members to radeon_llvm_contextVincent Lejeune2012-09-281-0/+5
* r600g: tgsi-to-llvm path is taken after declarations have been parsedVincent Lejeune2012-09-281-26/+32
* r600g: fix EXP on CaymanMarek Olšák2012-09-271-4/+2
* r600g: fix RSQ of negative value on CaymanMarek Olšák2012-09-271-0/+5
* r600g: Fix build with LLVM compilerTom Stellard2012-09-211-1/+1
* r600g: don't snoop context state while building shadersMarek Olšák2012-09-221-12/+18
* r600g: Use LOOP_START_DX10 for loopsTom Stellard2012-09-191-1/+3
* radeon/llvm: Emit ISA for ALU instructions in the R600 code emitterMichal Sciubidlo2012-09-191-28/+32
* r600g: Close a memory leak of llvm byte streamsXinya Zhang2012-09-171-0/+1
* r600g: add clip_misc_state for clip registers emitted in draw_vboMarek Olšák2012-09-131-2/+1
* Remove useless checks for NULL before freeingMatt Turner2012-09-051-4/+2
* Don't cast the return value of malloc/reallocMatt Turner2012-09-051-1/+1
* r600g: make F2U trans-only on r600-r700Marek Olšák2012-08-161-1/+1
* r600g: Glue to handle predicate aware output from llvmVincent Lejeune2012-08-151-11/+22
* r600g: Add support for predicatesVincent Lejeune2012-08-151-3/+5
* r600g: implement TXQ_LZ opcodeMarek Olšák2012-08-151-7/+15
* r600g: implement alpha-to-oneMarek Olšák2012-08-151-1/+2
* radeon/llvm: Use correct opcocde for BREAK_LOGICALNZ_i32Tom Stellard2012-08-141-11/+15
* r600g: fix F2U opcode translationDave Airlie2012-08-041-1/+1
* radeon/llvm: Fix a bug with IF LOGICALNZ with int operandVincent Lejeune2012-07-231-8/+12
* r600g: don't check the R600_GLSL130 env varMarek Olšák2012-07-151-1/+1
* radeon/llvm: Emit raw ISA for vertex fetch instructionsTom Stellard2012-06-291-20/+40
* r600g: avoid unnecessary shader exports v2Vadim Girlin2012-06-271-3/+22
* r600g: cache shader variants instead of rebuilding v3Vadim Girlin2012-06-271-10/+9
* r600g: Fix reading vtx instruction offset from bytestreamTom Stellard2012-06-211-1/+1
* r600g: Compute support for CaymanTom Stellard2012-06-061-0/+3
* radeon/llvm: Emit 2 bytes for vertex fetch offsetsTom Stellard2012-06-011-0/+2
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