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* r600g: fix inconsistency with INTERP* opcode definitionsVadim Girlin2012-01-241-5/+5
| | | | | Signed-off-by: Vadim Girlin <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* r600g: add missing opcode definitionsVadim Girlin2012-01-241-5/+85
| | | | | Signed-off-by: Vadim Girlin <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* r600g: add FLT_TO_UINT opcode for evergreenVadim Girlin2012-01-151-1/+1
| | | | Signed-off-by: Vadim Girlin <[email protected]>
* r600g: fix the representation of control-flow instructionsMarek Olšák2011-11-151-125/+139
| | | | | | | | | | | | | | | | | | | | | | | | | | We need something that looks like a compiler and not like some hacker put some functions together. /rant This is a band-aid for these two problems: - The R600 and EG control-flow instructions appear in switch statements next to each other, causing conflicts when adding new instructions. - The ALU control-flow instructions are bitshifted by 3 (from CF_INST 26:29 to CF_INST 23:29, as is defined by r600 ISA) even for EG, where CF_INST is 22:29. To fix this mess, the 'inst' field is bitshifted to the left either by 22, 23, or 26 (directly in the definitions), such that it can be just or'd when making bytecode without any shifting. All switch statements have been divided into two, one for R600 and the other for EG. Of course, there is a better way to do this, but that is left for future work. Tested on RV730 and REDWOOD with no regressions. v2: minor cleanup as per Alex's comment. Reviewed-by: Alex Deucher <[email protected]>
* r600g: add flat non-interpolation support.Dave Airlie2011-09-161-1/+1
| | | | | | | | | TGSI CONSTANT interpolation is just flat, and we just read the values direct from the LDS into the GPR without doing any interpolation on them. This is needed to pass integer types into the fragment shader. Signed-off-by: Dave Airlie <[email protected]>
* r600g: Replace the CHIPREV_* defines with the chip_class enum.Henri Verbeet2011-07-091-8/+2
| | | | Signed-off-by: Henri Verbeet <[email protected]>
* r600g: remove duplicate opcode in r600_opcodes.hAlex Deucher2011-05-251-1/+0
| | | | | | | | V_SQ_CF_WORD1_SQ_CF_INST_HALT is 0x1f on both evergreen and cayman. Reported-by: Gustaw Smolarczyk <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* r600g: add initial cayman acceleration support.Dave Airlie2011-05-251-10/+32
| | | | | | | | | | | | | | | | Cayman is the RadeonHD 69xx series of GPUs. This adds support for 3D acceleration to the r600g driver. Major changes: Some context registers moved around - mainly MSAA and clipping/guardband related. GPR allocation is all dynamic no vertex cache - all unified in texture cache. 5-wide to 4-wide shader engines (no scalar or trans slot) - some changes to how instructions are placed into slots - removal of END_OF_PROGRAM bit in favour of END flow control clause - no vertex fetch clause - TC accepts vertex or texture Signed-off-by: Dave Airlie <[email protected]>
* r600g: compiler helper opcode fixes for evergreenAlex Deucher2011-01-141-0/+4
| | | | Signed-off-by: Alex Deucher <[email protected]>
* r600g: use meaningful defines for chiprevAlex Deucher2010-11-191-2/+7
| | | | Makes the code much clearer.
* r600g: add evergreen ARL support.Dave Airlie2010-10-171-6/+2
| | | | | | Thanks to Alex Deucher for pointing out the FLT to int conversion is necessary and writing an initial patch, this brings about 20 piglits, and I think this is the last piece to make evergreen and r600 equal in terms of features.
* r600g: add initial evergreen supportDave Airlie2010-09-101-2/+220
| | | | | | | | | | adds shader opcodes + assembler support (except ARL) uses constant buffers add interp instructions in fragment shader adds all evergreen hw states adds evergreen pm4 support. this runs gears for me on my evergreen
* r600g: split opcodes out and add wrapper around usage.Dave Airlie2010-09-081-0/+178
This splits the r600 opcodes out of the sq file and adds a wrapper so we can convert to evergreen opcodes later without touching these functions too much.