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path: root/src/gallium/drivers/r600/r600_asm.h
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* r600g: Add support for predicatesVincent Lejeune2012-08-151-1/+3
| | | | Signed-off-by: Tom Stellard <[email protected]>
* r600g: Add FC_NATIVE instructionTom Stellard2012-05-021-0/+9
| | | | | | | This is a pseudo instruction that enables the LLVM backend to encode instructions and pass it through r600_bytecode_build() Signed-off-by: Tom Stellard <[email protected]>
* r600g: cleanup includesMarek Olšák2012-03-051-0/+2
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* r600g: merge r600_context with r600_pipe_contextMarek Olšák2012-01-311-2/+2
| | | | The split made no sense.
* r600g: remove u8,u16,u32,u64 typesMarek Olšák2012-01-311-3/+3
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* r600g: improve kcache line sets handling v2Vadim Girlin2012-01-211-1/+3
| | | | | | | | | Add support for multiple kcache banks (constant buffers). Lock the required lines only. Allow up to 4 kcache line sets in the alu clause by using ALU_EXTENDED on eg+. Signed-off-by: Vadim Girlin <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* r600g: fixup AR handling (v5)Dave Airlie2012-01-201-1/+8
| | | | | | | | | | | | | | | | | | | | | | | So it appears R600s (except rv670) do AR handling different using a different opcode. This patch fixes up r600g to work properly on r600. This fixes ~100 piglit tests here (in GLSL1.30 mode) on rv610. v3: add index_mode as per the docs. This still fails any dst relative tests for some reason I can't quite see yet, but it passes a lot more tests than without. v4: add a nop after dst.rel this could be improved using a second pass, where we only insert nops if two instructions are sure to collide. The docs say r600, rv610, rv630 needs this, and not rv670, rs780, rs880, need AMD to confirm rv620, rv635. v5: add is_nop_inst. NOTE: This is a candidate for stable branches. Signed-off-by: Dave Airlie <[email protected]>
* r600g: implement transform feedbackMarek Olšák2011-12-171-0/+2
| | | | | | | | r600: DONE. r700: MOSTLY (done but locks up). Evergreen: MOSTLY (done but doesn't work for an unknown reason). The kernel support will come soon.
* r600g: fix the representation of control-flow instructionsMarek Olšák2011-11-151-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | We need something that looks like a compiler and not like some hacker put some functions together. /rant This is a band-aid for these two problems: - The R600 and EG control-flow instructions appear in switch statements next to each other, causing conflicts when adding new instructions. - The ALU control-flow instructions are bitshifted by 3 (from CF_INST 26:29 to CF_INST 23:29, as is defined by r600 ISA) even for EG, where CF_INST is 22:29. To fix this mess, the 'inst' field is bitshifted to the left either by 22, 23, or 26 (directly in the definitions), such that it can be just or'd when making bytecode without any shifting. All switch statements have been divided into two, one for R600 and the other for EG. Of course, there is a better way to do this, but that is left for future work. Tested on RV730 and REDWOOD with no regressions. v2: minor cleanup as per Alex's comment. Reviewed-by: Alex Deucher <[email protected]>
* r600g: lazy load for AR registerVadim Girlin2011-11-131-0/+2
| | | | | | Emit MOVA* instruction only when AR is used. Signed-off-by: Vadim Girlin <[email protected]>
* r600g: rename bc -> bytecodeMarek Olšák2011-08-161-35/+35
| | | | It took me a while to figure out what it stands for.
* r600g: cleanup includes in winsysMarek Olšák2011-08-161-2/+0
| | | | Reviewed-by: Alex Deucher <[email protected]>
* r600g: Store the chip class directly in r600_bc.Henri Verbeet2011-07-091-2/+1
| | | | | | Instead of deriving it from the family again. Signed-off-by: Henri Verbeet <[email protected]>
* r600g: Replace the CHIPREV_* defines with the chip_class enum.Henri Verbeet2011-07-091-1/+1
| | | | Signed-off-by: Henri Verbeet <[email protected]>
* r600g: add initial cayman acceleration support.Dave Airlie2011-05-251-0/+2
| | | | | | | | | | | | | | | | Cayman is the RadeonHD 69xx series of GPUs. This adds support for 3D acceleration to the r600g driver. Major changes: Some context registers moved around - mainly MSAA and clipping/guardband related. GPR allocation is all dynamic no vertex cache - all unified in texture cache. 5-wide to 4-wide shader engines (no scalar or trans slot) - some changes to how instructions are placed into slots - removal of END_OF_PROGRAM bit in favour of END flow control clause - no vertex fetch clause - TC accepts vertex or texture Signed-off-by: Dave Airlie <[email protected]>
* r600g: add big endian support for r6xx/r7xxCédric Cano2011-04-191-0/+1
| | | | | Signed-off-by: Cedric Cano <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* r600g: Move fetch shader register setup to r600_state.c / evergreen_state.c.Henri Verbeet2011-03-141-1/+0
| | | | Signed-off-by: Henri Verbeet <[email protected]>
* r600g: split R600 and R700 CF generation for VTX and TEXChristian König2011-03-091-0/+1
| | | | Reviewed-by: Henri Verbeet <[email protected]>
* r600g: implement instanced drawing supportChristian König2011-02-281-1/+2
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* r600g: Split r600_bc_alu_src.Henri Verbeet2011-02-071-1/+1
| | | | | | The r600_bc_alu_src structure is used in two different ways, as a vector and for the individual channels of that same vector. This is somewhat fragile, and probably confusing.
* r600g: Store literal values in the r600_bc_alu_src structure.Henri Verbeet2011-02-071-1/+1
| | | | | This is much easier to work with, and allows use to get rid of some of the literal handling hacks.
* r600g: Make some more things static.Henri Verbeet2011-02-031-1/+0
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* r600g: Get rid of the unused r600_cf_vtx_tc() function.Henri Verbeet2011-02-031-1/+0
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* r600g: use burst exports in shadersChristian König2011-02-021-0/+1
| | | | | Join multiple exports into just one instruction instead of exporting each register separately.
* r600g: rework literal handlingChristian König2011-01-131-4/+2
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* r600g: merge alu groupsChristian König2011-01-131-0/+1
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* r600g: implement replacing gpr with pv and psChristian König2011-01-131-1/+1
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* r600g: rework bank swizzle codeChristian König2011-01-131-4/+0
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* r600g: implement output modifiers and use them to further optimize LRPChristian König2011-01-121-0/+1
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* r600g: Store kcache settings as an array.Henri Verbeet2011-01-071-6/+7
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* r600g: build fetch shader from vertex elementsJerome Glisse2010-12-061-0/+8
| | | | | | | | | | | | Vertex elements change are less frequent than draw call, those to avoid rebuilding fetch shader to often build the fetch shader along vertex elements. This also allow to move vertex buffer setup out of draw path and make update to it less frequent. Shader update can still be improved to only update SPI regs (based on some rasterizer state like flat shading or point sprite ...). Signed-off-by: Jerome Glisse <[email protected]>
* r600g: dump raw shader output for debuggingJerome Glisse2010-12-031-0/+1
| | | | Signed-off-by: Jerome Glisse <[email protected]>
* r600g: add fetch shader capabilitiesJerome Glisse2010-11-191-0/+1
| | | | | | | | Use fetch shader instead of having fetch instruction in the vertex shader. Allow to restrict shader update to a smaller part when vertex buffer input layout changes. Signed-off-by: Jerome Glisse <[email protected]>
* r600g: code cleanup (indent, trailing space, empty line ...)Jerome Glisse2010-11-171-7/+7
| | | | Signed-off-by: Jerome Glisse <[email protected]>
* r600g: add assembler support for all the kcache fields.Dave Airlie2010-10-261-0/+5
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* r600g: Also clear bc data when we're destroying a shader.Tilman Sauerbeck2010-10-241-0/+1
| | | | | | | [airlied: remove unused vars] Signed-off-by: Tilman Sauerbeck <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* r600g: drop use_mem_constant.Dave Airlie2010-10-051-1/+0
| | | | since we plan on using dx10 constant buffers everywhere.
* r600g: indentation fixesJerome Glisse2010-10-011-1/+1
| | | | Signed-off-by: Jerome Glisse <[email protected]>
* r600g: add assembler support for other vtx fetch fields.Dave Airlie2010-10-011-0/+5
| | | | | this shouldn't change behaviour, just push the choice of what to do out to the shader.
* r600g: more cleanupJerome Glisse2010-09-291-0/+7
| | | | Signed-off-by: Jerome Glisse <[email protected]>
* r600g; add uses waterfall to asm cf for r6xx.Dave Airlie2010-09-191-0/+1
| | | | On r6xx if an MOVA instruction is emitted we should set this bit.
* r600g: misc cleanupJohn Doe2010-09-151-26/+24
| | | | | | | Avoid using r600_screen structure to get ptr to radeon winsys structure. Signed-off-by: Jerome Glisse <[email protected]>
* r600g: add initial evergreen supportDave Airlie2010-09-101-0/+1
| | | | | | | | | | adds shader opcodes + assembler support (except ARL) uses constant buffers add interp instructions in fragment shader adds all evergreen hw states adds evergreen pm4 support. this runs gears for me on my evergreen
* r600g: add initial bank swizzle support.Dave Airlie2010-09-081-0/+7
| | | | | this is ported from r600c mostly, bank swizzling is real messy and I don't think I got enough sleep last night to fully understand it.
* r600g: add support for constants in memory buffers.Dave Airlie2010-09-081-0/+2
| | | | | | DX9 constants were in the constant file, and evergreen no longer support cfile. r600/700 can also use constants in memory buffers, so add the code (disabled for now) to enable that as precursor for evergreen.
* r600g: add initial relative support to assemblerDave Airlie2010-08-301-0/+2
| | | | | | passes another ~20 piglits. /me starts to run out low hanging fruit around now.
* r600g : add basic loop support.Dave Airlie2010-08-301-1/+16
| | | | | | Adds BGNLOOP, BRK, CONT, ENDLOOP support, ported from r600c. 17 piglits more on r300g.tests.
* r600g: add initial if/else/endif supportDave Airlie2010-08-271-1/+20
| | | | | | | | | this adds handling for some more CF instructions and conditions also adds parameter for stack size emission These seem to pass on VS with the stack size hack but not on FS, TODO: fix FS + stack size calcs
* r600g: add a chiprev type for r600/r700/evergreen instead of using familyDave Airlie2010-08-191-0/+1
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* r600g: avoid reemiting literal, avoid scheduling empty csJerome Glisse2010-08-101-0/+1
| | | | Signed-off-by: Jerome Glisse <[email protected]>
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