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path: root/src/gallium/drivers/r600/r600_asm.c
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* r600g: fix inconsistency with INTERP* opcode definitionsVadim Girlin2012-01-241-3/+3
* r600g: replace raw opcodes with names in the is_alu_trans/vectorVadim Girlin2012-01-241-12/+80
* r600g: shift integer ops are trans unit only on r600.Dave Airlie2012-01-221-0/+1
* r600g: replace trans/vector-only instruction lists with ranges (v2)Vadim Girlin2012-01-221-71/+15
* Revert "r600g: replace trans/vector-only instruction lists with ranges"Dave Airlie2012-01-221-11/+73
* r600g: take into account kcache banks for bank swizzle checkVadim Girlin2012-01-221-2/+2
* r600g: replace trans/vector-only instruction lists with rangesVadim Girlin2012-01-221-73/+11
* r600g: improve kcache line sets handling v2Vadim Girlin2012-01-211-84/+148
* r600g: make INTERP_LOAD_P0 vector-onlyVadim Girlin2012-01-211-0/+1
* r600g: fixup AR handling (v5)Dave Airlie2012-01-201-5/+90
* r600g: fix recip_uint on r600.Dave Airlie2012-01-181-0/+1
* r600g: rework IDIV/UDIV and implement MOD/UMOD (v2)Vadim Girlin2012-01-171-0/+2
* r600g: add support for ISHR/USHR/SHL on r600-evergreenVadim Girlin2012-01-151-4/+7
* r600g: add FLT_TO_UINT opcode for evergreenVadim Girlin2012-01-151-0/+3
* r600g: add r600 version of UINT_TO_FLT conversion.Dave Airlie2012-01-141-0/+1
* r600g: add missing case for uint->flt conversion.Dave Airlie2012-01-141-0/+1
* r600g: implement transform feedbackMarek Olšák2011-12-171-0/+115
* r600g: don't change the order of writes in merge_inst_groupVadim Girlin2011-11-171-1/+14
* r600g: fix the representation of control-flow instructionsMarek Olšák2011-11-151-201/+376
* r600g: fix op3 & write in merge_inst_groupsVadim Girlin2011-11-141-1/+1
* r600g: set max max tex/vtx instructions count to 16 for caymanAlex Deucher2011-11-141-3/+1
* r600g: set max tex/vtx instructions count to 16 for evergreenVadim Girlin2011-11-141-1/+1
* r600g: properly handle cayman in is_alu_vec_unit_inst()Alex Deucher2011-11-131-7/+15
* r600g: lazy load for AR registerVadim Girlin2011-11-131-0/+35
* r600g: include INTERP_[XY|ZW] in is_alu_vec_unit_instVadim Girlin2011-11-131-1/+3
* r600g: more integer supportDave Airlie2011-11-031-1/+15
* r600g: make r[67]00 not bail out on PRED_SETNE_INT.Mathias Fröhlich2011-10-231-0/+1
* r600g: make if's use PRED_SETNE_INT no matter what.Dave Airlie2011-10-221-0/+1
* r600g: print inst in hex in dumpsDave Airlie2011-10-221-6/+6
* r600g: uarl fixes.Dave Airlie2011-10-091-0/+3
* r600g/eg: add integer types supportDave Airlie2011-10-091-7/+15
* r600g: merge r600_bo with r600_resourceMarek Olšák2011-09-301-5/+7
* r600g: add flat non-interpolation support.Dave Airlie2011-09-161-0/+1
* r600g: add initial evergreen integer opcode supportDave Airlie2011-09-061-2/+23
* r600g: add 10/10/10/2 vertex format conversion.Dave Airlie2011-09-051-0/+6
* r600g: fix replace_gpr_with_pv_psVadim Girlin2011-08-251-1/+1
* r600g: fix check_and_set_bank_swizzleVadim Girlin2011-08-251-10/+20
* r600g: rename bc -> bytecodeMarek Olšák2011-08-161-134/+134
* r600g: remove an unused parameter from r600_bo_destroyMarek Olšák2011-08-161-1/+1
* r600g: use buffer_map/unmap from radeon_winsysMarek Olšák2011-08-161-1/+1
* r600g: Add support for ROUND, v2Lauri Kasanen2011-08-101-0/+2
* r600g: Store the chip class directly in r600_bc.Henri Verbeet2011-07-091-44/+4
* r600g: Replace the CHIPREV_* defines with the chip_class enum.Henri Verbeet2011-07-091-68/+68
* r600g: Store the chip class in r600_pipe_context.Henri Verbeet2011-07-091-2/+2
* r600g: eg+ support for FS_COLOR0_WRITES_ALL_CBUFSAlex Deucher2011-06-241-0/+2
* r600g: add TXD support.Dave Airlie2011-06-151-0/+3
* r600g: Put shaders into immutable buffers.Mathias Fröhlich2011-06-131-1/+1
* gallium: s/bool/boolean/Brian Paul2011-06-081-2/+2
* r600g: prepare for passing ctx into _r600_pipe_state_add_regDave Airlie2011-06-021-2/+2
* r600g: add llano supportAlex Deucher2011-05-311-0/+2
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