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path: root/src/gallium/drivers/r600/r600_asm.c
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* r600g: Use LOOP_START_DX10 for loopsTom Stellard2012-09-191-1/+7
* radeon/llvm: Emit ISA for ALU instructions in the R600 code emitterMichal Sciubidlo2012-09-191-0/+43
* r600g: fix relative addressing on RS780 and RS880Marek Olšák2012-08-281-7/+6
* r600g: Fix instruction group merge when there are predicated insts.Vincent Lejeune2012-08-151-0/+18
* radeon/llvm: Do not use PV/PS if PRED_SEL does not matchVincent Lejeune2012-08-151-2/+4
* r600g: Add support for predicatesVincent Lejeune2012-08-151-5/+7
* r600g: Update number of gprs when adding a vertex instructionTom Stellard2012-07-091-0/+4
* r600g: add RECIP_INT, PRED_SETE_INT to r600_bytecode_get_num_operandsVadim Girlin2012-05-251-0/+2
* r600g: Handle MUL_IEEE in r600_bytecode_get_num_operandsTom Stellard2012-05-171-0/+2
* gallium/drivers: handle TGSI_OPCODE_CEILChristoph Bumiller2012-05-091-0/+2
* r600g: Print integer values of literal constants in shader dumpsTom Stellard2012-05-031-1/+2
* r600g: Add support for reading BREAK_LOGICALZ_i32 from bytestreamTom Stellard2012-05-031-0/+1
* r600g: fixed the bug with VTX fetches in TEX clauses for evergreenAdam Rak2012-05-021-7/+6
* r600g: Add FC_NATIVE instructionTom Stellard2012-05-021-0/+7
* winsys/radeon: simplify buffer map/unmap functionsMarek Olšák2012-04-291-2/+2
* r600g: fix gpr number calculationVadim Girlin2012-04-231-0/+3
* r600g: kill off the fallback for crazy src_offset valuesMarek Olšák2012-04-041-16/+8
* r600g: cleanup includesMarek Olšák2012-03-051-8/+5
* r600g: remove obsolete todo commentsMarek Olšák2012-03-051-1/+1
* r600g: merge r600_context with r600_pipe_contextMarek Olšák2012-01-311-2/+2
* r600g: remove u8,u16,u32,u64 typesMarek Olšák2012-01-311-2/+2
* r600g: fix inconsistency with INTERP* opcode definitionsVadim Girlin2012-01-241-3/+3
* r600g: replace raw opcodes with names in the is_alu_trans/vectorVadim Girlin2012-01-241-12/+80
* r600g: shift integer ops are trans unit only on r600.Dave Airlie2012-01-221-0/+1
* r600g: replace trans/vector-only instruction lists with ranges (v2)Vadim Girlin2012-01-221-71/+15
* Revert "r600g: replace trans/vector-only instruction lists with ranges"Dave Airlie2012-01-221-11/+73
* r600g: take into account kcache banks for bank swizzle checkVadim Girlin2012-01-221-2/+2
* r600g: replace trans/vector-only instruction lists with rangesVadim Girlin2012-01-221-73/+11
* r600g: improve kcache line sets handling v2Vadim Girlin2012-01-211-84/+148
* r600g: make INTERP_LOAD_P0 vector-onlyVadim Girlin2012-01-211-0/+1
* r600g: fixup AR handling (v5)Dave Airlie2012-01-201-5/+90
* r600g: fix recip_uint on r600.Dave Airlie2012-01-181-0/+1
* r600g: rework IDIV/UDIV and implement MOD/UMOD (v2)Vadim Girlin2012-01-171-0/+2
* r600g: add support for ISHR/USHR/SHL on r600-evergreenVadim Girlin2012-01-151-4/+7
* r600g: add FLT_TO_UINT opcode for evergreenVadim Girlin2012-01-151-0/+3
* r600g: add r600 version of UINT_TO_FLT conversion.Dave Airlie2012-01-141-0/+1
* r600g: add missing case for uint->flt conversion.Dave Airlie2012-01-141-0/+1
* r600g: implement transform feedbackMarek Olšák2011-12-171-0/+115
* r600g: don't change the order of writes in merge_inst_groupVadim Girlin2011-11-171-1/+14
* r600g: fix the representation of control-flow instructionsMarek Olšák2011-11-151-201/+376
* r600g: fix op3 & write in merge_inst_groupsVadim Girlin2011-11-141-1/+1
* r600g: set max max tex/vtx instructions count to 16 for caymanAlex Deucher2011-11-141-3/+1
* r600g: set max tex/vtx instructions count to 16 for evergreenVadim Girlin2011-11-141-1/+1
* r600g: properly handle cayman in is_alu_vec_unit_inst()Alex Deucher2011-11-131-7/+15
* r600g: lazy load for AR registerVadim Girlin2011-11-131-0/+35
* r600g: include INTERP_[XY|ZW] in is_alu_vec_unit_instVadim Girlin2011-11-131-1/+3
* r600g: more integer supportDave Airlie2011-11-031-1/+15
* r600g: make r[67]00 not bail out on PRED_SETNE_INT.Mathias Fröhlich2011-10-231-0/+1
* r600g: make if's use PRED_SETNE_INT no matter what.Dave Airlie2011-10-221-0/+1
* r600g: print inst in hex in dumpsDave Airlie2011-10-221-6/+6
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