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path: root/src/gallium/drivers/r600/evergreend.h
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* r600: add register info for atomic counters.Dave Airlie2017-06-061-0/+47
| | | | | | | | | The atomic counters on evergreen are implemented via append/consume UAV counters. This just adds the register info for them. The EOS packets are used to get the atomic totals extracted post shader execution for storing into a buffer. Reviewed-by: Glenn Kennard <[email protected]>
* r600: add missing RAT registers and operations.Dave Airlie2017-06-061-0/+12
| | | | | | | | | | This just documents in the headers the RAT operation list, and the RAT encoding for exports. The immediate registers are used to point to buffers for the RAT return values (_RTN instructions). Reviewed-by: Glenn Kennard <[email protected]>
* r600: fix incorrect and missing bit field in register headers.Dave Airlie2017-06-051-3/+4
| | | | | The compression field was incorrect, and we were missing the depth before shader field.
* r600/eg: add support for tracing IBs after a hang.Dave Airlie2017-06-011-3/+12
| | | | | | | | | This is a poor man's version of radeonsi ddebug stuff, this should get hooked into that infrastructure, and grow more stuff, but for now, just create R600_TRACE var that points to a file that you want to dump the last IB to. Signed-off-by: Dave Airlie <[email protected]>
* r600g: Add scratch ring register definesGlenn Kennard2017-05-121-0/+14
| | | | | Acked-by: Dave Airlie <[email protected]> Signed-off-by: Glenn Kennard <[email protected]>
* amd: normalize register definition formattingMarek Olšák2017-03-301-15/+45
| | | | | | | This resolves trivial conflicts with gfx9d.h caused by different formatting. Some fields are also renamed. Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/radeon: set VPORT_ZMIN/MAX registers correctlyMarek Olšák2016-09-051-2/+2
| | | | | | | | | | | | Calculate depth ranges from viewport states and pipe_rasterizer_state::clip_halfz. The evergreend.h change is required to silence a warning. This fixes this recently updated piglit: arb_depth_clamp/depth-clamp-range Reviewed-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* r600g: fix CP DMA hazard with index buffer fetches (v3)Marek Olšák2016-06-041-0/+1
| | | | | | | | | v3: use PFP_SYNC_ME on EG-CM only when supported by the kernel, otherwise use MEM_WRITE + WAIT_REG_MEM to emulate that Reviewed-by: Alex Deucher <[email protected]> Tested-by: Grazvydas Ignotas <[email protected]> Tested-by: Dieter Nützel <[email protected]>
* gallium/radeon: clean left-shift undefined behaviorNicolai Hähnle2016-05-071-552/+552
| | | | | | | | | | | | | | Shifting into the sign bit of a signed int is undefined behavior. Unfortunately, there are potentially many places where this happens using the register macros. This commit is the result of running sed -ie "s/(((\(\w\+\)) & 0x\(\w\+\)) << \(\w\+\))/(((unsigned)(\1) \& 0x\2) << \3)/g" on all header files in gallium/{r600,radeon,radeonsi}. Reviewed-by: Marek Olšák <[email protected]>
* r600g: clean up aniso state translationMarek Olšák2016-04-121-7/+7
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* r600g: implement set_active_query_state for pausing occlusion queriesMarek Olšák2016-04-121-1/+1
| | | | | | | Use ZPASS_INCREMENT_DISABLE everywhere. Reviewed-by: Edward O'Callaghan <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* r600: fix masks for two of the unused evergreen regs.Dave Airlie2015-12-071-2/+2
| | | | Signed-off-by: Dave Airlie <[email protected]>
* r600: fixes for register definitions.Dave Airlie2015-11-301-3/+3
| | | | | | Forgot to add these. Signed-off-by: Dave Airlie <[email protected]>
* r600: add missing register to initial stateDave Airlie2015-11-301-1/+0
| | | | | | | | | | We really should initialise HS/LS_2 and SQ_LDS_ALLOC exists on all evergreen not just cayman, so we should initialise it as well. Reviewed-by: Glenn Kennard <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* r600: define registers required for tessellationDave Airlie2015-11-301-27/+105
| | | | | | | | | This adds the defines for a bunch of registers and shader values that are required to implement tessellation. Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Glenn Kennard <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* r600: initialised PGM_RESOURCES_2 for ES/GSDave Airlie2015-11-121-0/+2
| | | | | | | | | | | This fixes the corruption on rendering that we are seeing in certain geometry shaders. Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=91780 Reviewed-by: Alex Deucher <[email protected]> Tested / Reviewed-by: Glenn Kennard <[email protected]> Cc: "10.6" "11.0" <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* r600g: Pass conservative depth parameters to hwGlenn Kennard2015-11-111-0/+7
| | | | | | | | Supported on R700 and up. Signed-off-by: Glenn Kennard <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* Revert "r600g: Pass conservative depth parameters to hw"Dave Airlie2015-11-111-7/+0
| | | | | | This reverts commit a1fc78911e9a6439db94d6ae91d5672c76e5fb1c. I pushed the wrong patch.
* r600g: Pass conservative depth parameters to hwGlenn Kennard2015-11-111-0/+7
| | | | | | | Supported on R700 and up. Signed-off-by: Glenn Kennard <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* r600: define some values for the fetch constant offsets.Dave Airlie2015-09-121-0/+8
| | | | | | | | This just puts these in one place and #defines them. Reviewed-by: Glenn Kennard <[email protected]> Reviewed-by: Edward O'Callaghan <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* r600,compute: setup compute sampler states and viewsZoltan Gilian2015-08-141-0/+5
| | | | | | | | v2: Add compute mode flag to sampler state setup (Marek). Drop branches which avoid reference counting (Marek). Simplify unset branch condition (Marek). Reviewed-by: Marek Olšák <[email protected]>
* r600g: Implement GL_ARB_draw_indirect for EG/CMGlenn Kennard2015-02-241-1/+0
| | | | | | | | | | | | | | | | Requires Evergreen/Cayman and radeon kernel module 2.41.0 or newer. Expected piglit fails due to hardware limitations: * arb_draw_indirect-draw-arrays-prim-restart Restarts not applied for DrawArrays commands * arb_draw_indirect-vertexid Base vertex offset is not included in vertex id Marek: bump vgt_state num_dw by 3 (= space needed for one register write) Signed-off-by: Glenn Kennard <[email protected]> Signed-off-by: Marek Olšák <[email protected]>
* r600g: Implement GL_ARB_sample_shadingGlenn Kennard2014-10-121-0/+3
| | | | | | | | Also fixes two sided lighting which was broken at least on pre-evergreen by commit b1eb00. Signed-off-by: Glenn Kennard <[email protected]> Signed-off-by: Marek Olšák <[email protected]>
* r600g: clear constant buffer sizes at the beginning of CSMarek Olšák2014-08-141-0/+1
| | | | Reviewed-by: Alex Deucher <[email protected]>
* r600g: use TGSI_PROPERTY to disable viewport and clippingChristoph Bumiller2014-06-021-0/+28
| | | | | | | | | | v2 get rid of magic value, use DEFINES v3 update clip_disable together with vs_position_window_space Big thanks to Marek Olšák! Signed-off-by: David Heidelberger <[email protected]> Signed-off-by: Marek Olšák <[email protected]>
* r600g: fix hang on RV740 by using DX_RASTERIZATION_KILL instead of SX_MISCMarek Olšák2014-04-251-0/+3
| | | | | | | | Changing SX_MISC hangs RV740. When we're at it, let's use DX_RASTERIZATION_KILL on all R700 and later chipsets. Cc: 10.0 10.1 [email protected] Reviewed-by: Alex Deucher <[email protected]>
* r600g: deobfuscate async DMA codeMarek Olšák2014-03-201-0/+4
| | | | Reviewed-by: Michel Dänzer <[email protected]>
* r600g: add primitive input support for gsDave Airlie2014-02-051-0/+4
| | | | | | | only enable prim id if gs uses it Signed-off-by: Dave Airlie <[email protected]> Reviewed-by: Alex Deucher <[email protected]>
* r600g: add hw register definitions for GS block setupVadim Girlin2014-02-051-6/+74
| | | | | Signed-off-by: Dave Airlie <[email protected]> Reviewed-by: Alex Deucher <[email protected]>
* r600g/compute: Emit DEALLOC_STATE on cayman after dispatching a compute shader.Tom Stellard2014-01-271-0/+1
| | | | | | | | | | | | This is necessary to prevent the next SURFACE_SYNC packet from hanging the GPU. https://bugs.freedesktop.org/show_bug.cgi?id=73418 Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Alex Deucher <[email protected]> CC: "9.2" "10.0" <[email protected]>
* r600g: move streamout state to drivers/radeonMarek Olšák2013-08-311-8/+8
| | | | | | | | | | | | | | | | | | | | | | | | This streamout state code will be used by radeonsi. There are new structures r600_common_context and r600_common_screen. What is inherited by what is shown here: pipe_context -> r600_common_context -> r600_context pipe_screen -> r600_common_screen -> r600_screen The common structures reside in drivers/radeon. Currently they only contain enough functionality to be able to handle streamout. Eventually I'd like the whole pipe_screen implementation to be shared and some of the context stuff too. This is quite big, but most changes are because of the new structures and the fact r600_write_value is replaced by radeon_emit. Thanks to Tom Stellard for fixing the build for r600g/compute. Reviewed-by: Michel Dänzer <[email protected]> Reviewed-by: Christian König <[email protected]> Tested-by: Tom Stellard <[email protected]>
* r600g: rewrite FMASK allocation, fix FMASK texturing with 2 and 4 samplesMarek Olšák2013-05-151-0/+3
| | | | | | | | | | | | This fixes and enables texturing with compressed MSAA colorbuffers on Evergreen and Cayman. For the first time, multisample textures work on Cayman. This requires the libdrm flag RADEON_SURF_FMASK. v2: require libdrm_radeon 2.4.45 Reviewed-by: Alex Deucher <[email protected]>
* r600g: Add evergreen_emit_cs_constant_buffers() v2Tom Stellard2013-04-251-0/+2
| | | | | | | | v2: - Bump R600_NUM_ATOMS Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* r600g: use CP DMA for buffer clears on evergreen+Alex Deucher2013-04-241-0/+42
| | | | | | | | | | Lighter weight then using streamout. Only evergreen and newer asics support embedded data as src with CP DMA. Reviewed-by: Jerome Glisse <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* r600g: atomize pixel shaderMarek Olšák2013-03-111-0/+1
| | | | Reviewed-by: Jerome Glisse <[email protected]>
* r600g: add async for staging buffer upload v2Jerome Glisse2013-01-281-0/+15
| | | | | | v2: Add virtual address to dma src/dst offset for cayman Signed-off-by: Jerome Glisse <[email protected]>
* r600g: add htile support v16Jerome Glisse2012-12-201-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | htile is used for HiZ and HiS support and fast Z/S clears. This commit just adds the htile setup and Fast Z clear. We don't take full advantage of HiS with that patch. v2 really use fast clear, still random issue with some tiles need to try more flush combination, fix depth/stencil texture decompression v3 fix random issue on r6xx/r7xx v4 rebase on top of lastest mesa, disable CB export when clearing htile surface to avoid wasting bandwidth v5 resummarize htile surface when uploading z value. Fix z/stencil decompression, the custom blitter with custom dsa is no longer needed. v6 Reorganize render control/override update mecanism, fixing more issues in the process. v7 Add nop after depth surface base update to work around some htile flushing issue. For htile to 8x8 on r6xx/r7xx as other combination have issue. Do not enable hyperz when flushing/uncompressing depth buffer. v8 Fix htile surface, preload and prefetch setup. Only set preload and prefetch on htile surface clear like fglrx. Record depth clear value per level. Support several level for the htile surface. First depth clear can't be a fast clear. v9 Fix comments, properly account new register in emit function, disable fast zclear if clearing different layer of texture array to different value v10 Disable hyperz for texture array making test simpler. Force db_misc_state update when no depth buffer is bound. Remove unused variable, rename depth_clearstencil to depth_clear. Don't allocate htile surface for flushed depth. Something broken the cliprect change, this need to be investigated. v11 Rebase on top of newer mesa v12 Rebase on top of newer mesa v13 Rebase on top of newer mesa, htile surface need to be initialized to zero, somehow special casing first clear to not use fast clear and thus initialize the htile surface with proper value does not work in all case. v14 Use resource not texture for htile buffer make the htile buffer size computation easier and simpler. Disable preload on evergreen as its still troublesome in some case v15 Cleanup some comment and remove some left over v16 Define name for bit 20 of CP_COHER_CNTL Signed-off-by: Pierre-Eric Pelloux-Prayer <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Signed-off-by: Jerome Glisse <[email protected]>
* r600g: add in-place DB decompression and texturing with DB tilingMarek Olšák2012-11-061-3/+7
| | | | | | | | | | | | | | | | | | | | | The decompression is done in-place and only the compressed tiles are decompressed. Note: R6xx-R7xx can do that only with Z16 and Z32F. The texture unit is programmed to use non-displayable tiling and depth ordering of samples, so that it can fetch the texture in the native DB format. The latest version of the libdrm surface allocator is required for stencil texturing to work. The old one didn't create the mipmap tree correctly. We need a separate mipmap tree for stencil, because the stencil mipmap offsets are not really depth offsets/4. There are still some known bugs, but this should save some memory and it also improves performance a little bit in Lightsmark (especially with low resolutions; tested with Radeon HD 5000). The DB->CB copy is still used for transfers. Reviewed-by: Jerome Glisse <[email protected]>
* r600g: use SQ_VTX_SEMANTIC_CLEAR to clear the semantic registersMarek Olšák2012-10-311-0/+1
| | | | Reviewed-by: Alex Deucher <[email protected]>
* r600g: implement texturing with 8x MSAA compressed surfaces for EvergreenMarek Olšák2012-10-291-1/+1
| | | | | | | | | | The 2x and 4x MSAA cases are completely broken. The lfdptr instruction returns garbage there. The 8x MSAA case is broken on Cayman, though at least the result looks somewhat correct. Only the 8x MSAA case works on Evergreen and is enabled.
* r600g/compute: always CONTEXT_CONTROL packet at start of CSAlex Deucher2012-10-261-0/+1
| | | | | | | | | | It's required. The CP uses this to properly allocate new contexts. Also do a CS partial flush since we are updating CONFIG regs which are single state. Signed-off-by: Alex Deucher <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Tom Stellard <[email protected]>
* r600g: Add register field definitions for 028C70_RESOURCE_TYPETom Stellard2012-10-011-0/+7
| | | | Reviewed-by: Marek Olšák <[email protected]>
* r600g: use invalid DB hardware formats to disable depth/stencilMarek Olšák2012-09-271-0/+2
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* r600g: add support for geometry shader samplers and constant buffersMarek Olšák2012-09-131-0/+2
| | | | Reviewed-by: Jerome Glisse <[email protected]>
* r600g: simplify flushingMarek Olšák2012-09-131-5/+2
| | | | | | | | | | | | Based on the patch called "simplify and fix flushing and synchronization" by Jerome Glisse. Rebased, removed unneded code, simplified more and cleaned up. Also, SH_ACTION_ENA is not set when changing shaders (hw doesn't seem to need it). It's only used to flush constant buffers. Reviewed-by: Jerome Glisse <[email protected]>
* r600g: adjust QUANT_MODE for higher precisionVadim Girlin2012-09-041-0/+11
| | | | | | | | | Use 1/256 for R6xx/7xx, 1/4096 for evergreen, instead of default 1/16. Helps to pass some piglit tests (fbo, multisample). Signed-off-by: Vadim Girlin <[email protected]> Reviewed-by: Alex Deucher <[email protected]>
* r600g: implement MSAA for CaymanMarek Olšák2012-08-311-0/+21
| | | | | Everything works except for blitting MSAA colorbuffers, which isn't so trivial on Cayman. It's a rarely-used feature anyway.
* r600g: implement compression for MSAA colorbuffers for evergreenMarek Olšák2012-08-271-9/+67
| | | | | | | | | | | | | | | | This adds the FMASK and CMASK buffers. They share the same resource with color data. COMPRESSION and FAST_CLEAR are always enabled if both FMASK and CMASK are allocated. We initialize the CMASK to a "compressed" state (not "fast cleared"), so that we can keep FAST_CLEAR enabled all the time. Both FMASK and CMASK must be present at the moment. If either one is missing, the other one is not used. v2: add cayman regs in the list Reviewed-by: Jerome Glisse <[email protected]>
* r600g: implement MSAA rendering and texturing for evergreen and caymanMarek Olšák2012-08-151-2/+22
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* r600g: implement alpha-to-coverageMarek Olšák2012-08-151-0/+7
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