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* r600: Add support for loading index register from other than chan XGert Wollny2020-05-191-1/+1
| | | | | | Signed-off-by: Gert Wollny <[email protected]> Reviewed-by: Reviewed-by: Dave Airlie <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5085>
* r600g: Support emitting scratch opsGlenn Kennard2018-02-091-1/+2
| | | | | Signed-off-by: Glenn Kennard <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* r600/eg: make sure we allow vpm bit on other CF ops.Dave Airlie2018-02-011-0/+1
| | | | | | | the vpm bit wasn't being applied to the push/pop instructions. Reviewed-by: Roland Scheidegger <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* r600: emit 0 gds_op for tf write.Dave Airlie2018-01-181-2/+3
| | | | | | | This field is ignored for tf writes so should be 0. Reviewed-by: Roland Scheidegger <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* r600: Emit EOP for more CF instruction typesGert Wollny2017-11-221-4/+9
| | | | | | | | | | | | | | | | | | | | So far on pre-cayman chipsets the CF instructions CF_OP_LOOP_END, CF_OP_CALL_FS, CF_OP_POP, and CF_OP_GDS an extra CF_NOP instruction was added to add the EOP flag, even though this is not actually needed, because all these instrutions support the EOP flag. This patch removes the fixup code, adds setting the EOP flag for the according instructions as well as others like CF_OP_TEX and CF_OP_VTX, and adds writing out EOP for this type of instruction in the disassembler. This also fixes a bug where shaders were created that didn't actually have the EOP flag set in the last CF instruction, which might have resulted in GPU lockups. [airlied: cleaned up a little] Signed-off-by: Gert Wollny <[email protected]> Cc: <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* r600: add support for emitting RAT instructions to the assembler.Dave Airlie2017-11-031-0/+19
| | | | | | | | This adds support for emitting RAT instructions to the assembler. RAT instructions are used to implement image accessors. Reviewed-by: Nicolai Hähnle <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* r600: add support for mark bit to the assembler.Dave Airlie2017-11-031-0/+2
| | | | | | | | This adds support to the assembler for the mark bit on the export word1. Reviewed-by: Nicolai Hähnle <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* r600: add support for valid pixel mode on CF clausesDave Airlie2017-11-031-0/+1
| | | | | | | | This just adds support to the assembler for setting the valid pixel mode on the CF clause. Reviewed-by: Nicolai Hähnle <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* r600/asm: add support for other GDS operations.Dave Airlie2017-06-261-3/+12
| | | | | | | This adds support for the GDS operations needed to do atomic counters. Signed-off-by: Dave Airlie <[email protected]>
* r600: add support for LDS instruction encoding.Dave Airlie2015-12-071-0/+75
| | | | | | | | | | These are used in tessellation shaders to read/write values between VS/TCS/TES. This splits the eg alu assembler out to handle these instructions. Signed-off-by: Dave Airlie <[email protected]>
* r600: add support for GDS clause to the assembler.Dave Airlie2015-12-071-0/+23
| | | | | | | This just adds enough for the tessellation shaders, which require TF_WRITE to work. Signed-off-by: Dave Airlie <[email protected]>
* r600g: add support for streams to the assembler.Dave Airlie2015-09-021-0/+1
| | | | | | | | This just adds support to the assembler dumper and allows stream instructions to be generated. Also fix up the stream debugging to add stream info. Signed-off-by: Dave Airlie <[email protected]>
* r600g: fix sampler/ubo indexing on caymanDave Airlie2015-07-111-6/+11
| | | | | | | | | | Cayman needs a different method to upload the CF IDX0/1 This fixes 31 piglits when ARB_gpu_shader5 is forced on with cayman. Reviewed-by: Glenn Kennard <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* r600g: Implement sm5 UBO/sampler indexingGlenn Kennard2014-10-281-4/+48
| | | | | | | | | Caveat: Shaders using UBO/sampler indexing will not be optimized by SB, due to SB not currently supporting the necessary CF_INDEX_[01] index registers. Signed-off-by: Glenn Kennard <[email protected]>
* r600g: initial support for geometry shaders on evergreen (v2)Vadim Girlin2014-02-051-4/+5
| | | | | | | | | | | | | | This is Vadim's initial work with a few regression fixes squashed in. v2: (airlied) fix regression in glsl-max-varyings - need to use vs and ps_dirty fix regression in shader exports from rebasing. whitespace fixing. v2.1: squash fix assert Signed-off-by: Vadim Girlin <[email protected]> Signed-off-by: Dave Airlie <[email protected]> Reviewed-by: Alex Deucher <[email protected]>
* r600g/bc: add support for indexed memory writes.Dave Airlie2014-02-051-2/+4
| | | | | | | It looks like we need these for geom shaders in the future. Signed-off-by: Dave Airlie <[email protected]> Reviewed-by: Alex Deucher <[email protected]>
* r600g: move barrier and end_of_program bits from output to cf struct (v2)Vadim Girlin2014-02-051-4/+6
| | | | | | | | v2: fix regression on r600 NOP instructions. Signed-off-by: Vadim Girlin <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* r600g: use tables with ISA info v3Vadim Girlin2013-02-011-104/+78
| | | | | | | | | v3: added some flags including condition codes for ALU, fixed issue with CF reverse lookup (overlapping ranges of CF_ALU_xxx and other CF instructions) rebased on current master Signed-off-by: Vadim Girlin <[email protected]>
* r600g/llvm: tgsi to llvm emits stream output intrinsics.Vincent Lejeune2013-01-181-0/+2
| | | | Reviewed-by: Tom Stellard <[email protected]>
* r600g: make tgsi-to-llvm generates store.pixel* intrinsic for fsVincent Lejeune2012-11-021-0/+17
| | | | Reviewed-by: Tom Stellard <thomas.stellard at amd.com>
* r600g: move shader structures into r600_shader.hMarek Olšák2012-10-121-0/+1
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* r600g: Use LOOP_START_DX10 for loopsTom Stellard2012-09-191-0/+1
| | | | | | | | | | LOOP_START_DX10 ignores the LOOP_CONFIG* registers, so it is not limited to 4096 iterations like the other LOOP_* instructions. Compute shaders need to use this instruction, and since we aren't optimizing loops with the LOOP_CONFIG* registers for pixel and vertex shaders, it seems like we should just use it for everything. Reviewed-by: Marek Olšák <[email protected]>
* r600g: Add FC_NATIVE instructionTom Stellard2012-05-021-0/+4
| | | | | | | This is a pseudo instruction that enables the LLVM backend to encode instructions and pass it through r600_bytecode_build() Signed-off-by: Tom Stellard <[email protected]>
* r600g: cleanup includesMarek Olšák2012-03-051-6/+4
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* r600g: improve kcache line sets handling v2Vadim Girlin2012-01-211-0/+17
| | | | | | | | | Add support for multiple kcache banks (constant buffers). Lock the required lines only. Allow up to 4 kcache line sets in the alu clause by using ALU_EXTENDED on eg+. Signed-off-by: Vadim Girlin <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* r600g: implement transform feedbackMarek Olšák2011-12-171-0/+29
| | | | | | | | r600: DONE. r700: MOSTLY (done but locks up). Evergreen: MOSTLY (done but doesn't work for an unknown reason). The kernel support will come soon.
* r600g: fix the representation of control-flow instructionsMarek Olšák2011-11-151-10/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | We need something that looks like a compiler and not like some hacker put some functions together. /rant This is a band-aid for these two problems: - The R600 and EG control-flow instructions appear in switch statements next to each other, causing conflicts when adding new instructions. - The ALU control-flow instructions are bitshifted by 3 (from CF_INST 26:29 to CF_INST 23:29, as is defined by r600 ISA) even for EG, where CF_INST is 22:29. To fix this mess, the 'inst' field is bitshifted to the left either by 22, 23, or 26 (directly in the definitions), such that it can be just or'd when making bytecode without any shifting. All switch statements have been divided into two, one for R600 and the other for EG. Of course, there is a better way to do this, but that is left for future work. Tested on RV730 and REDWOOD with no regressions. v2: minor cleanup as per Alex's comment. Reviewed-by: Alex Deucher <[email protected]>
* r600g: rename bc -> bytecodeMarek Olšák2011-08-161-1/+1
| | | | It took me a while to figure out what it stands for.
* r600g: Replace the CHIPREV_* defines with the chip_class enum.Henri Verbeet2011-07-091-1/+1
| | | | Signed-off-by: Henri Verbeet <[email protected]>
* r600g: add initial cayman acceleration support.Dave Airlie2011-05-251-3/+7
| | | | | | | | | | | | | | | | Cayman is the RadeonHD 69xx series of GPUs. This adds support for 3D acceleration to the r600g driver. Major changes: Some context registers moved around - mainly MSAA and clipping/guardband related. GPR allocation is all dynamic no vertex cache - all unified in texture cache. 5-wide to 4-wide shader engines (no scalar or trans slot) - some changes to how instructions are placed into slots - removal of END_OF_PROGRAM bit in favour of END flow control clause - no vertex fetch clause - TC accepts vertex or texture Signed-off-by: Dave Airlie <[email protected]>
* r600g: Move fetch shader register setup to r600_state.c / evergreen_state.c.Henri Verbeet2011-03-141-12/+0
| | | | Signed-off-by: Henri Verbeet <[email protected]>
* r600g: implement instanced drawing supportChristian König2011-02-281-24/+2
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* r600g: use burst exports in shadersChristian König2011-02-021-1/+2
| | | | | Join multiple exports into just one instruction instead of exporting each register separately.
* r600g: optimize away CF_INST_POPChristian König2011-01-121-0/+2
| | | | | If last instruction is an CF_INST_ALU we don't need to emit an additional CF_INST_POP for stack clean up after an IF ELSE ENDIF.
* r600g: Store kcache settings as an array.Henri Verbeet2011-01-071-6/+6
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* r600g: build fetch shader from vertex elementsJerome Glisse2010-12-061-0/+35
| | | | | | | | | | | | Vertex elements change are less frequent than draw call, those to avoid rebuilding fetch shader to often build the fetch shader along vertex elements. This also allow to move vertex buffer setup out of draw path and make update to it less frequent. Shader update can still be improved to only update SPI regs (based on some rasterizer state like flat shading or point sprite ...). Signed-off-by: Jerome Glisse <[email protected]>
* r600g: add fetch shader capabilitiesJerome Glisse2010-11-191-0/+2
| | | | | | | | Use fetch shader instead of having fetch instruction in the vertex shader. Allow to restrict shader update to a smaller part when vertex buffer input layout changes. Signed-off-by: Jerome Glisse <[email protected]>
* r600g: add assembler support for all the kcache fields.Dave Airlie2010-10-261-1/+6
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* r600g: indentation fixesJerome Glisse2010-10-011-2/+2
| | | | Signed-off-by: Jerome Glisse <[email protected]>
* r600g: delete old pathJerome Glisse2010-09-291-5/+4
| | | | | | Lot of clean can now happen. Signed-off-by: Jerome Glisse <[email protected]>
* r600g: misc cleanupJohn Doe2010-09-151-0/+1
| | | | | | | Avoid using r600_screen structure to get ptr to radeon winsys structure. Signed-off-by: Jerome Glisse <[email protected]>
* r600g: add initial evergreen supportDave Airlie2010-09-101-0/+84
adds shader opcodes + assembler support (except ARL) uses constant buffers add interp instructions in fragment shader adds all evergreen hw states adds evergreen pm4 support. this runs gears for me on my evergreen
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