| Commit message (Collapse) | Author | Age | Files | Lines |
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Missed a few drivers in the earlier changes, this should fix up all the
ones that print unknown caps or don't have a default statement.
Signed-off-by: Ilia Mirkin <[email protected]>
Reviewed-by: Dave Airlie <[email protected]>
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v2: add alignment restrictions to docs, fix indentation in headers
Reviewed-by: Christian König <[email protected]>
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v2: incorporated changes from Marek Olšák
Reviewed-by: Marek Olšák <[email protected]>
Signed-off-by: David Heidelberg <[email protected]>
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Resolving a multisampled depth texture into
a single sampled texture is supported on >= SM4.1
hw. It is possible some previous hw support it.
The ability was tested on radeonsi and nvc0.
Apparently is is also supported for radeon >= r700.
This patch adds the MULTISAMPLE_Z_RESOLVE cap and
add it to the drivers. It is advertised for drivers
for which it is sure the ability is supported.
Reviewed-by: Marek Olšák <[email protected]>
Signed-off-by: Axel Davy <[email protected]>
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Signed-off-by: Ilia Mirkin <[email protected]>
Reviewed-by: Glenn Kennard <[email protected]>
Reviewed-by: Roland Scheidegger <[email protected]>
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The code was exactly the same, except util/ has c++ guards and a struct
simple_node declaration.
Reviewed-by: Marek Olšák <[email protected]>
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Same as ARL, just has extra rounding.
Useful for st/nine.
Tested-by: Pavel Ondračka <[email protected]>
Reviewed-by: Marek Olšák <[email protected]>
Signed-off-by: David Heidelberg <[email protected]>
Reviewed-by: Alex Deucher <[email protected]>
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Plus a new PIPE_CAP_VERTEXID_NOBASE query. The idea is that drivers not
supporting vertex ids with base vertex offset applied (so, only support
d3d10-style vertex ids) will get such a d3d10-style vertex id instead -
with the caveat they'll also need to handle the basevertex system value
too (this follows what core mesa already does).
Additionally, this is also useful for other state trackers (for instance
llvmpipe / draw right now implement the d3d10 behavior on purpose, but
with different semantics it can just do both).
Doesn't do anything yet.
And fix up the docs wrt similar values.
v2: incorporate feedback from Brian and others, better names, better docs.
Reviewed-by: Brian Paul <[email protected]>
Reviewed-by: Jose Fonseca <[email protected]>
Reviewed-by: Marek Olšák <[email protected]>
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Android builds Mesa from git, so there don't need to be in the tarball.
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Required by Nine. Tested with util_run_tests.
It's added to softpipe, llvmpipe, and r300g/swtcl.
Tested-by: David Heidelberg <[email protected]>
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Nothing in the tree generates it.
Reviewed-by: Jose Fonseca <[email protected]>
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Never generated, and implemented in only nvfx vertprog.
Reviewed-by: Jose Fonseca <[email protected]>
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Nothing generated them.
Reviewed-by: Jose Fonseca <[email protected]>
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Reviewed-by: Jose Fonseca <[email protected]>
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Nothing in the tree generates it.
Reviewed-by: Jose Fonseca <[email protected]>
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Nothing in the tree generated it.
v2: Only drop ARA, not ARR as well.
Reviewed-by: Jose Fonseca <[email protected]> (v2)
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Nothing in the tree generated it.
Reviewed-by: Jose Fonseca <[email protected]>
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They weren't generated in tree, and as far as I know all hardware had to
lower it to a DP, RSQ, MUL.
Reviewed-by: Jose Fonseca <[email protected]>
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This switch statement's code structure isn't dependent on the numbers of
the opcodes at all.
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I forgot that we cannot emit vertex shader state on a chip without VS.
In such a case, clip_halfz is handled by the Draw module.
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In preparation of ARB_clip_control. Let the driver decide if
it supports pipe_rasterizer_state::clip_halfz being set to true.
v3:
Initially enable on ilo.
Reviewed-by: Roland Scheidegger <[email protected]>
Reviewed-by: Brian Paul <[email protected]>
Signed-off-by: Mathias Froehlich <[email protected]
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Reviewed-by: Alex Deucher <[email protected]>
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With 5 shader stages and various combinations of enabled and disabled shaders,
the maximum number of outputs in one shader doesn't have to be equal to
the maximum number of inputs in the following shader.
v2: return 32 for softpipe and llvmpipe
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This code is already in if (!variable->C->is_r500) so no need check
twice.
Reviewed-by: Tom Stellard <[email protected]>
Signed-off-by: David Heidelberger <[email protected]>
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Originally the variables were set only once via the ?= operator but
that causes issues when doing incremental builds. They appear to be
undefined and missing from the dependency list despite their addition
to LIBADD.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=84807
Signed-off-by: Emil Velikov <[email protected]>
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Reviewed-by: Roland Scheidegger <[email protected]>
v2: fix svga too
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Use an array of properties indexed by TGSI_PROPERTY_* definitions.
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There's no other way. It will use hw resolve + blit.
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Rather than duplicating the libdeps, extra define... all over the
targets, define them only once and use when applicable.
Signed-off-by: Emil Velikov <[email protected]>
Acked-by: Christian König <[email protected]>
Acked-by: Matt Turner <[email protected]>
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The definition of rc_pair_regalloc_inputs_only() is no longer
around so drop the declaration.
Signed-off-by: Emil Velikov <[email protected]>
Reviewed-by: Marek Olšák <[email protected]>
Acked-by: Matt Turner <[email protected]>
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The r300 gallium driver is using it outside of the Mesa tree, and I wanted
to do so for vc4 as well. Rather than make the multiple-definitions
problem even more complicated, just move it to more-shared code.
v2: Don't forget to delete the symlink in r300 (review by Matt).
Delete more r300-helper references (review by Emil)
Don't prefix util/ header inclusion with "util/" (review by Emil)
Reviewed-by: Matt Turner <[email protected]> (v1)
Reviewed-by: Emil Velikov <[email protected]> (v1)
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In commit 567e2769b81863b6dffdac3826a6b729ce6ea37c ("ra: make the p, q
test more efficient") I unknowingly introduced a new requirement to the
register allocator API: the user must set the register class of all
nodes before setting up their interferences, because
ra_add_conflict_list() now uses the classes of the two interfering
nodes. i965 already did this, but r300g was setting up register classes
interleaved with setting up the interference graph. This led to us
calculating the wrong q total, and in certain cases
e78a01d5e6f77e075fe667a0f0ccb10d89c0dd58 (" ra: optimistically color
only one node at a time") made it so that this bug caused a segfault. In
particular, the error occurred if the q total was decremented to 1 below
0 for the last node to be pushed onto the stack. Since q_total is an
unsigned integer, it overflowed to 0xffffffff, which is what
lowest_q_total happens to be initialzed to. This means that we would
fail the "new_q_total < lowest_q_total" check on line 476 of
register_allocate.c, and so the node would never be pushed onto the
stack, which led to segfaults in ra_select() when we failed to ever give
it a register.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=82828
Cc: "10.3" <[email protected]>
Signed-off-by: Connor Abbott <[email protected]>
Tested-by: Pavel Ondračka <[email protected]>
Reviewed-by: Tom Stellard <[email protected]>
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This allows a sampler view to have a different texture target than the
underlying resource. This will be used to implement the type casting
between 2d arrays and cube maps as specified in ARB_texture_view.
Signed-off-by: Ilia Mirkin <[email protected]>
Reviewed-by: Roland Scheidegger <[email protected]>
Reviewed-by: Marek Olšák <[email protected]>
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- include all headers in Makefile.sources
- sort the list(s)
- bundle the android buildscript & the tests
Signed-off-by: Emil Velikov <[email protected]>
Acked-by: Matt Turner <[email protected]>
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Did this code mean to do something else, you tell me!
Reviewed-by: Marek Olšák <[email protected]>
Signed-off-by: Dave Airlie <[email protected]>
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- Add top_srcdir/src/gallium/winsys to GALLIUM_DRIVER_C{XXFLAGS}.
- Remove top_srcdir/src/gallium/drivers/radeon from the includes.
As a result:
- Common radeon headers are prefixed with 'radeon/'
- Winsys header inclusion is prefixed 'radeon/drm'
Cc: Marek Olšák <[email protected]>
Cc: Michel Dänzer <[email protected]>
Signed-off-by: Emil Velikov <[email protected]>
Reviewed-by: Marek Olšák <[email protected]>
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Signed-off-by: Timothy Arceri <[email protected]>
Reviewed-by: Roland Scheidegger <[email protected]>
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Reviewed-by: Michel Dänzer <[email protected]>
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Fixes make check in that case.
Reviewed-by: Tom Stellard <[email protected]>
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Reviewed-by: Ilia Mirkin <[email protected]>
Reviewed-by: Roland Scheidegger <[email protected]>
Signed-off-by: Tobias Klausmann <[email protected]>
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Signed-off-by: Emil Velikov <[email protected]>
Reviewed-by: Marek Olšák <[email protected]>
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Signed-off-by: Ilia Mirkin <[email protected]>
Reviewed-by: Marek Olšák <[email protected]> (v1)
Reviewed-by: Roland Scheidegger <[email protected]> (v1)
v2: Reuse opcode gaps as suggested by Marek
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Fixes piglit glean "do-loop with continue and break" on RS690
It's based on Tom Stellard patch and improved to handle CMP instruction.
[v2] handle CMP instruction
Reviewed-by: Tom Stellard <[email protected]>
Signed-off-by: David Heidelberger <[email protected]>
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Previously, there were 3 entrypoints into parts of the actual allocator,
and an API called ra_allocate_no_spills() that called all 3. Nobody
would ever want to call any of the 3 entrypoints by themselves, so
everybody just used ra_allocate_no_spills(). So just make them static
functions, and while we're at it rename ra_allocate_no_spills() to
ra_allocate() since there's no equivalent "with spills," because the
backend is supposed to handle spilling.
Signed-off-by: Connor Abbott <[email protected]>
Reviewed-by: Eric Anholt <[email protected]>
Reviewed-by: Kenneth Graunke <[email protected]>
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- include the correct folders
- add a new buildscript for the common radeon folder
v2: Use the installed libdrm headers over the DRM_TOP ones.
Cc: "10.1 10.2" <[email protected]>
[Emil Velikov] Split up and add commit message.
Signed-off-by: Emil Velikov <[email protected]>
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The link error occurs because the static libraries are linked in the wrong
order. This fixes it.
Signed-off-by: Jason Ekstrand <[email protected]>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=82483
Reviewed-by: Tom Stellard <[email protected]>
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This limit is fixed in Mesa core and cannot be changed.
It only affects ARB_vertex_program and ARB_fragment_program.
The minimum value for ARB_vertex_program is 1 according to the spec.
The maximum value for ARB_vertex_program is limited to 1 by Mesa core.
The value should be zero for ARB_fragment_program, because it doesn't
support ARL.
Finally, drivers shouldn't mess with these values arbitrarily.
Reviewed-by: Ilia Mirkin <[email protected]>
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Trivial.
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