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* mesa: Restore 78-column wrapping of license text in C-style comments.Kenneth Graunke2013-04-2323-92/+92
| | | | | | | | | | | | | | The previous commit introduced extra words, breaking the formatting. This text transformation was done automatically via the following shell command: $ git grep 'THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY' | sed 's/:.*$//' | xargs -I {} sh -c 'vim -e -s {} < vimscript where 'vimscript' is a file containing: /THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY/;/\*\// !fmt -w 78 -p ' * ' :wq Reviewed-by: Brian Paul <[email protected]>
* mesa: Add "OR COPYRIGHT HOLDERS" to license text disclaiming liability.Kenneth Graunke2013-04-2323-23/+23
| | | | | | | | | | | | | | | This brings the license text in line with the MIT License as published on the Open Source Initiative website: http://opensource.org/licenses/mit-license.php Generated automatically be the following shell command: $ git grep 'THE AUTHORS BE LIABLE' | sed 's/:.*$//g' | xargs -I '{}' \ sed -i 's/THE AUTHORS/THE AUTHORS OR COPYRIGHT HOLDERS/' {} This introduces some wrapping issues, to be fixed in the next commit. Reviewed-by: Brian Paul <[email protected]>
* gallium: Replace gl_rasterization_rules with lower_left_origin and ↵José Fonseca2013-04-231-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | half_pixel_center. Squashed commit of the following: commit 04c5fa2cbb8e89d6f2fa5a75af1cca03b1f6b852 Author: José Fonseca <[email protected]> Date: Tue Apr 23 17:37:18 2013 +0100 gallium: s/lower_left_origin/bottom_edge_rule/ commit 4dff4f64fa83b9737def136fffd161d55e4f1722 Author: José Fonseca <[email protected]> Date: Tue Apr 23 17:35:04 2013 +0100 gallium: Move diagram to docs. commit 442a63012c8c3c3797f45e03f2ca20ad5f399832 Author: James Benton <[email protected]> Date: Fri May 11 17:50:55 2012 +0100 gallium: Replace gl_rasterization_rules with lower_left_origin and half_pixel_center. This change is necessary to achieve correct results when using OpenGL FBOs. Reviewed-by: Marek Olšák <[email protected]>
* st/mesa: optionally apply texture swizzle to border color v2Christoph Bumiller2013-04-181-0/+2
| | | | | | | | | | | | This is the only sane solution for nv50 and nvc0 (really, trust me), but since on other hardware the border colour is tightly coupled with texture state they'd have to undo the swizzle, so I've added a cap. The dependency of update_sampler on the texture updates was introduced to avoid doing the apply_depthmode to the swizzle twice. v2: Moved swizzling helper to u_format.c, extended the CAP to provide more accurate information.
* gallium: Disambiguate TGSI_OPCODE_IF.José Fonseca2013-04-171-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | TGSI_OPCODE_IF condition had two possible interpretations: - src.x != 0.0f - Mesa statetracker when PIPE_SHADER_CAP_INTEGERS was false either for vertex and fragment shaders - gallivm/llvmpipe - postprocess - vl state tracker - vega state tracker - most old drivers - old internal state trackers - many graw examples - src.x != 0U - Mesa statetracker when PIPE_SHADER_CAP_INTEGERS was true for both vertex and fragment shaders - tgsi_exec/softpipe - r600 - radeonsi - nv50 And drivers that use draw module also were a mess (because Mesa would emit float IFs, but draw module supports native integers so it would interpret IF arg as integers...) This sort of works if the source argument is limited to float +0.0f or +1.0f, integer 0, but would fail if source is float -0.0f, or integer in the float NaN range. It could also fail if source is integer 1, and hardware flushes denormalized numbers to zero. But with this change there are now two opcodes, IF and UIF, with clear meaning. Drivers that do not support native integers do not need to worry about UIF. However, for backwards compatibility with old state trackers and examples, it is advisable that native integer capable drivers also support the float IF opcode. I tried to implement this for r600 and radeonsi based on the surrounding code. I couldn't do this for nouveau, so I just shunted IF/UIF together, which matches the current behavior. Reviewed-by: Roland Scheidegger <[email protected]> Reviewed-by: Marek Olšák <[email protected]> v2: - Incorporate Roland's feedback. - Fix r600_shader.c merge conflict. - Fix typo in radeon, spotted by Michel Dänzer. - Incorporte Christoph Bumiller's patch to handle TGSI_OPCODE_IF(float) properly in nv50/ir.
* nvc0: set ret variable if launch desc allocation failedEmil Velikov2013-04-121-1/+3
| | | | | | | | | | | | | | | Pointed out by gcc nve4_compute.c: In function 'nve4_launch_grid': nve4_compute.c:511:7: warning: 'ret' may be used uninitialized in this function [-Wmaybe-uninitialized] if (ret) ^ Signed-off-by: Emil Velikov <[email protected]> Edit by Christoph Bumiller: Set it to -1 to indicate failure and only when it's actually required.
* nvc0: bail out early during nve4_compute_setup()Emil Velikov2013-04-121-1/+1
| | | | | | | Exit gracefully rather than trying to create a random object, whenever the chipset is unknown Signed-off-by: Emil Velikov <[email protected]>
* nvc0: compile nve4_cache_split_name() only in debug buildEmil Velikov2013-04-121-1/+1
| | | | | | | | | | As otherwise it is unused - pointed out by gcc nve4_compute.c:586:20: warning: 'nve4_cache_split_name' defined but not used [-Wunused-function] static const char *nve4_cache_split_name(unsigned value) ^ Signed-off-by: Emil Velikov <[email protected]>
* nvc0: implement multisample texturesChristoph Bumiller2013-04-126-19/+73
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* nvc0: patch up TEX cases with 5 or 6 sources on nve4Christoph Bumiller2013-04-121-1/+19
| | | | Hackishly fixes alignment requirement of 2nd tuple for now.
* nvc0: fix 2D engine MS2 resolveChristoph Bumiller2013-04-121-2/+2
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* nv50,nvc0: remove MS resolve formats hackChristoph Bumiller2013-04-031-10/+0
| | | | Mesa now allows BlitFramebuffer resolve between RGBA and BGRA.
* nvc0: fix 128 bit compressed storage type selectionChristoph Bumiller2013-04-031-1/+1
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* nvc0: place staging textures in GART and map them directlyChristoph Bumiller2013-04-035-7/+72
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* nvc0: honour scaled coordiantes setting for linear texturesChristoph Bumiller2013-04-031-6/+5
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* nvc0: fix for 2d engine R source formats writing RRR1 and not R001Christoph Bumiller2013-04-031-28/+61
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* nv50,nvc0: disable DEPTH_RANGE_NEAR/FAR clipping during blitChristoph Bumiller2013-04-032-1/+3
| | | | | We send position.z == 0, DEPTH_RANGE may be some arbitrary range not including 0 (for exmaple in piglit's hiz tests).
* nouveau: accelerate buffer copies in resource_copy_regionChristoph Bumiller2013-04-031-3/+3
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* nvc0: demagic some of the NVE4_COMPUTE_UPLOAD methodsChristoph Bumiller2013-04-033-49/+129
| | | | It's actually the same as P2MF.
* nvc0: read PM counters for each warp scheduler separatelyChristoph Bumiller2013-04-032-61/+138
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* nvc0: add some metrics to driver specific queriesChristoph Bumiller2013-04-032-58/+160
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* nvc0: add some driver statistics queriesChristoph Bumiller2013-04-0310-25/+188
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* nvc0: disable compressed storage type 0xdb for nowChristoph Bumiller2013-04-031-1/+3
| | | | Single-sample color compression doesn't seem that useful anyway.
* nvc0: use correct hw query for PRIMITIVES_GENERATEDChristoph Bumiller2013-04-031-4/+7
| | | | It was the same as SO_STATISTICS[1] before.
* nvc0: use fence to check state of queries that don't write sequenceChristoph Bumiller2013-04-031-1/+5
| | | | | | This still isn't optimal, since the fence will signal a bit late, but better than checking on the bo, which may never be ready if it is shared (which is likely).
* gallium: add PIPE_CAP_QUERY_PIPELINE_STATISTICSChristoph Bumiller2013-04-031-0/+1
| | | | Reviewed-by: Marek Olšák <[email protected]>
* nvc0: Fix fd leak in nvc0_create_decoderMaarten Lankhorst2013-04-021-2/+2
| | | | | | NOTE: This is a candidate for the 9.0 and 9.1 branches. Signed-off-by: Maarten Lankhorst <[email protected]>
* nvc0: implement MP performance countersChristoph Bumiller2013-03-298-6/+556
| | | | | | | | | There's more, but this only adds (most) of the counters that are handled directly by the shader processors. The other counter domains are not handled on the multiprocessor and there are no FIFO object methods for configuring them. Instead, they have to be programmed by the kernel via PCOUNTER, and the interface for this isn't in place yet.
* nvc0: enable compression when supportedChristoph Bumiller2013-03-293-3/+13
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* nvc0: use NOUVEAU_GETPARAM_GRAPH_UNITS to get MP countChristoph Bumiller2013-03-294-29/+73
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* nv50,nvc0: fix 3d blits, restore viewport after blitChristoph Bumiller2013-03-291-16/+26
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* gallium,st/mesa: don't use blit-based transfers with software rasterizersMarek Olšák2013-03-231-0/+2
| | | | | | | | | The blit-based paths for TexImage, GetTexImage, and ReadPixels aren't very fast with software rasterizer. Now Gallium drivers have the ability to turn them off. Reviewed-by: Brian Paul <[email protected]> Tested-by: Brian Paul <[email protected]>
* nvc0: fix max varying count, move CLIPVERTEX,FOG out of the wayChristoph Bumiller2013-03-202-7/+18
| | | | | | The card spews an error if I use all 128 generic slots. Apparently the real limit isn't just dictated by the address space layout.
* gallium: add TGSI_SEMANTIC_TEXCOORD,PCOORD v3Christoph Bumiller2013-03-202-34/+4
| | | | | | | | | | | | | | | This makes it possible to identify gl_TexCoord and gl_PointCoord for drivers where sprite coordinate replacement is restricted. The new PIPE_CAP_TGSI_TEXCOORD decides whether these varyings should be hidden behind the GENERIC semantic or not. With this patch only nvc0 and nv30 will request that they be used. v2: introduce a CAP so other drivers don't have to bother with the new semantic v3: adapt to introduction gl_varying_slot enum
* nvc0: avoid crash on updating RASTERIZE_ENABLE stateChristoph Bumiller2013-03-122-4/+18
| | | | | When doing a blit with the 3D engine, the rasterizer or zsa cso may be NULL.
* nvc0: add MP trap handler for nve4Christoph Bumiller2013-03-124-15/+314
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* nvc0: they removed the NTID,NCTAID,GRIDID registers on nve4Christoph Bumiller2013-03-125-23/+65
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* nvc0: implement compute support for nve4Christoph Bumiller2013-03-1215-71/+1827
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* nvc0/ir: try to fix CAS (CompareAndSwap)Christoph Bumiller2013-03-122-1/+42
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* nv50/ir: add CCTL (cache control) opChristoph Bumiller2013-03-121-0/+25
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* nvc0/ir/emit: fix emission of large address offsetsChristoph Bumiller2013-03-121-8/+50
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* nv50/ir: add support for different sampler and resource index on nve4Christoph Bumiller2013-03-121-37/+22
| | | | | | | | | | And remove non-working code for indirect sampler/resource selection. Will be added back later. Includes code from "nv50/ir/tgsi: Resource indirect indexing" by Francisco Jerez (when mixing the R and S handles we can only specify them via a register, i.e. indirectly, unless we upload all the used handle combinations to c[] space, which we don't for now).
* nv50/ir: implement splitting of 64 bit ops after RAChristoph Bumiller2013-03-121-19/+12
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* nvc0/ir: skip back edges when determining latest sched valueChristoph Bumiller2013-03-121-3/+4
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* nvc0/ir: use large issue delay after RET, tooChristoph Bumiller2013-03-121-1/+1
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* nv50/ir: add support for barriersChristoph Bumiller2013-03-121-0/+96
| | | | nv50 part by Francisco Jerez.
* nvc0/ir: don't replace load from input in COMPUTE progs with VFETCHChristoph Bumiller2013-03-121-2/+7
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* nvc0/ir: implement lowering of surface ops for nve4Christoph Bumiller2013-03-122-3/+399
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* nvc0/ir: add formatted surface load lib code, move to extra headerChristoph Bumiller2013-03-126-149/+1309
| | | | | | OpenGL is nice and makes the user specify a format with an image unit. OpenCL is evil and doesn't, and what's better than adding a huge load of functions that we call indirectly to handle the conversion ?
* nvc0/ir: lower atomics in s[]Christoph Bumiller2013-03-121-0/+33
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