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path: root/src/gallium/drivers/nvc0/codegen
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* nv50/ir/opt: try to convert ABS(SUB) to SADChristoph Bumiller2012-04-292-1/+17
* nvc0/ir: try to use the optimal texture op modeChristoph Bumiller2012-04-291-3/+15
* nvc0/ir: initial implementation of nve4 scheduling hintsChristoph Bumiller2012-04-293-11/+597
* nvc0/ir: implement better placement of texture barriersChristoph Bumiller2012-04-291-7/+269
* nvc0/ir/emit: fix emitTXQ 2nd srcChristoph Bumiller2012-04-291-1/+3
* nvc0/ir/target: integer ADD doesn't support ABS modifierChristoph Bumiller2012-04-291-0/+2
* nvc0: add initial support for nve4+ (Kepler) chipsetsChristoph Bumiller2012-04-153-25/+110
* nv50/ir: import nv50 targetChristoph Bumiller2012-04-141-1/+1
* nv50/ir: fix off-by-ones in CSE and nvc0 insnCanLoadChristoph Bumiller2012-04-141-1/+1
* nv50/ir: rewrite the register allocator as GCRA, with spillingChristoph Bumiller2012-04-141-4/+2
* nvc0: fix emission of 3rd src in SET_AND,OR,XORChristoph Bumiller2012-04-141-0/+3
* nv50/ir: Decouple object cloning logic from the sub-object recursion policy.Francisco Jerez2012-04-141-2/+2
* nv50/ir: make Instruction::src/def container privateChristoph Bumiller2012-04-143-165/+171
* nv50/ir/opt: improve post-multiply and check target for supportChristoph Bumiller2012-04-142-0/+13
* nv50/ir: add isAccessSupported check for memory access coalescingChristoph Bumiller2012-04-143-1/+12
* nv50/ir: make use of TGSI_INTERPOLATE_COLORChristoph Bumiller2012-01-121-5/+0
* nvc0/ir: TXF array index already is an integerChristoph Bumiller2012-01-101-3/+6
* nvc0/ir/emit: fix modifiers of f32 add with long immediateChristoph Bumiller2012-01-101-5/+11
* nvc0/ir: fix default insertion position in pre-SSA lowering passChristoph Bumiller2012-01-101-7/+1
* nv50/ir: use RDSV to fetch FrontFacing before loweringChristoph Bumiller2011-10-211-13/+11
* nv50/ir: fix textureGrad with offsets and in non-FPsChristoph Bumiller2011-10-212-3/+11
* nv50/ir: add wrap mode for shift operationsChristoph Bumiller2011-10-211-2/+2
* nvc0/ir: fix emission of cvt when register and type size differChristoph Bumiller2011-10-211-2/+3
* nv50/ir: fix argument count for CUBE_ARRAY texture targetChristoph Bumiller2011-10-211-3/+3
* nvc0/ir: GP emit address must end up in $r0Christoph Bumiller2011-10-211-0/+4
* nvc0/ir: TXQ requires different lowering from normal TEXChristoph Bumiller2011-10-211-1/+10
* nvc0/ir: handle levelZero modifier in TEX emissionChristoph Bumiller2011-10-211-1/+9
* nvc0/ir: fix lowering of DIV F32Christoph Bumiller2011-10-211-0/+1
* nvc0/ir: fix xy confusion typo in readTessCoordChristoph Bumiller2011-10-211-1/+1
* nv50/ir: add missing license headersChristoph Bumiller2011-09-144-0/+84
* nv50/ir: import new shader backend codeChristoph Bumiller2011-09-144-0/+3033