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path: root/src/gallium/drivers/nvc0/codegen
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* nvc0: enable very initial support for nvf0 (GK110)Ben Skeggs2013-07-052-5/+66
* mesa: Restore 78-column wrapping of license text in C-style comments.Kenneth Graunke2013-04-235-20/+20
* mesa: Add "OR COPYRIGHT HOLDERS" to license text disclaiming liability.Kenneth Graunke2013-04-235-5/+5
* gallium: Disambiguate TGSI_OPCODE_IF.José Fonseca2013-04-171-1/+1
* nvc0: implement multisample texturesChristoph Bumiller2013-04-121-2/+3
* nvc0: patch up TEX cases with 5 or 6 sources on nve4Christoph Bumiller2013-04-121-1/+19
* nvc0: add MP trap handler for nve4Christoph Bumiller2013-03-122-0/+228
* nvc0: they removed the NTID,NCTAID,GRIDID registers on nve4Christoph Bumiller2013-03-122-2/+27
* nvc0/ir: try to fix CAS (CompareAndSwap)Christoph Bumiller2013-03-122-1/+42
* nv50/ir: add CCTL (cache control) opChristoph Bumiller2013-03-121-0/+25
* nvc0/ir/emit: fix emission of large address offsetsChristoph Bumiller2013-03-121-8/+50
* nv50/ir: add support for different sampler and resource index on nve4Christoph Bumiller2013-03-121-37/+22
* nv50/ir: implement splitting of 64 bit ops after RAChristoph Bumiller2013-03-121-19/+12
* nvc0/ir: skip back edges when determining latest sched valueChristoph Bumiller2013-03-121-3/+4
* nvc0/ir: use large issue delay after RET, tooChristoph Bumiller2013-03-121-1/+1
* nv50/ir: add support for barriersChristoph Bumiller2013-03-121-0/+96
* nvc0/ir: don't replace load from input in COMPUTE progs with VFETCHChristoph Bumiller2013-03-121-2/+7
* nvc0/ir: implement lowering of surface ops for nve4Christoph Bumiller2013-03-121-2/+380
* nvc0/ir: add formatted surface load lib code, move to extra headerChristoph Bumiller2013-03-126-149/+1309
* nvc0/ir: lower atomics in s[]Christoph Bumiller2013-03-121-0/+33
* nvc0/ir/emit: implement INSBF, EXTBF, PERMT and ATOMChristoph Bumiller2013-03-122-1/+133
* nvc0/ir/target: some ops can't be predicated, e.g. CALLChristoph Bumiller2013-03-121-0/+8
* nv50/ir: add support for indirect BRA,CALLChristoph Bumiller2013-03-121-2/+17
* nvc0/ir/emit: implement move to and logic ops on predicatesChristoph Bumiller2013-03-121-0/+45
* nvc0/ir/emit: implement surface related opsChristoph Bumiller2013-03-122-0/+301
* nv50/ir: initialize CodeEmitters' specialized target fieldsChristoph Bumiller2013-03-122-6/+6
* nv50/ir: add various new OPs that will be needed for computeChristoph Bumiller2013-03-121-3/+4
* nv50/ir: Rename "mkLoad" to "mkLoadv" for consistency.Francisco Jerez2013-03-121-2/+2
* nv50/nvc0: Build codegen in nv50.Johannes Obermayr2013-01-121-1/+1
* nvc0/ir: allow neg,abs modifiers on OP_SET with integer resultChristoph Bumiller2012-12-081-0/+4
* nvc0/ir/emit: fix check for flags register use in logic opsChristoph Bumiller2012-12-081-3/+3
* nv50,nvc0: add support for cube map arraysChristoph Bumiller2012-12-072-2/+0
* nvc0/ir: add initial code to support GK110 ISA encodingChristoph Bumiller2012-09-075-13/+1658
* nvc0/ir: allow 64-bit constant loads on nve4Christoph Bumiller2012-05-291-1/+1
* nvc0/ir: fix texture barrier insertion to prevent WAW hazardsChristoph Bumiller2012-05-292-21/+78
* nv50/ir: fix reversed order of lane ops in quadopsChristoph Bumiller2012-05-171-2/+3
* nvc0/ir: allow abs,neg source modifiers with ceil,floor,truncChristoph Bumiller2012-05-061-0/+3
* nvc0/ir: fix lowering of textureGradChristoph Bumiller2012-05-062-8/+9
* nv50/ir/opt: try to convert ABS(SUB) to SADChristoph Bumiller2012-04-292-1/+17
* nvc0/ir: try to use the optimal texture op modeChristoph Bumiller2012-04-291-3/+15
* nvc0/ir: initial implementation of nve4 scheduling hintsChristoph Bumiller2012-04-293-11/+597
* nvc0/ir: implement better placement of texture barriersChristoph Bumiller2012-04-291-7/+269
* nvc0/ir/emit: fix emitTXQ 2nd srcChristoph Bumiller2012-04-291-1/+3
* nvc0/ir/target: integer ADD doesn't support ABS modifierChristoph Bumiller2012-04-291-0/+2
* nvc0: add initial support for nve4+ (Kepler) chipsetsChristoph Bumiller2012-04-153-25/+110
* nv50/ir: import nv50 targetChristoph Bumiller2012-04-141-1/+1
* nv50/ir: fix off-by-ones in CSE and nvc0 insnCanLoadChristoph Bumiller2012-04-141-1/+1
* nv50/ir: rewrite the register allocator as GCRA, with spillingChristoph Bumiller2012-04-141-4/+2
* nvc0: fix emission of 3rd src in SET_AND,OR,XORChristoph Bumiller2012-04-141-0/+3
* nv50/ir: Decouple object cloning logic from the sub-object recursion policy.Francisco Jerez2012-04-141-2/+2