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* mesa: Restore 78-column wrapping of license text in C-style comments.Kenneth Graunke2013-04-2335-140/+140
| | | | | | | | | | | | | | The previous commit introduced extra words, breaking the formatting. This text transformation was done automatically via the following shell command: $ git grep 'THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY' | sed 's/:.*$//' | xargs -I {} sh -c 'vim -e -s {} < vimscript where 'vimscript' is a file containing: /THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY/;/\*\// !fmt -w 78 -p ' * ' :wq Reviewed-by: Brian Paul <[email protected]>
* mesa: Add "OR COPYRIGHT HOLDERS" to license text disclaiming liability.Kenneth Graunke2013-04-2335-35/+35
| | | | | | | | | | | | | | | This brings the license text in line with the MIT License as published on the Open Source Initiative website: http://opensource.org/licenses/mit-license.php Generated automatically be the following shell command: $ git grep 'THE AUTHORS BE LIABLE' | sed 's/:.*$//g' | xargs -I '{}' \ sed -i 's/THE AUTHORS/THE AUTHORS OR COPYRIGHT HOLDERS/' {} This introduces some wrapping issues, to be fixed in the next commit. Reviewed-by: Brian Paul <[email protected]>
* gallium: Replace gl_rasterization_rules with lower_left_origin and ↵José Fonseca2013-04-231-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | half_pixel_center. Squashed commit of the following: commit 04c5fa2cbb8e89d6f2fa5a75af1cca03b1f6b852 Author: José Fonseca <[email protected]> Date: Tue Apr 23 17:37:18 2013 +0100 gallium: s/lower_left_origin/bottom_edge_rule/ commit 4dff4f64fa83b9737def136fffd161d55e4f1722 Author: José Fonseca <[email protected]> Date: Tue Apr 23 17:35:04 2013 +0100 gallium: Move diagram to docs. commit 442a63012c8c3c3797f45e03f2ca20ad5f399832 Author: James Benton <[email protected]> Date: Fri May 11 17:50:55 2012 +0100 gallium: Replace gl_rasterization_rules with lower_left_origin and half_pixel_center. This change is necessary to achieve correct results when using OpenGL FBOs. Reviewed-by: Marek Olšák <[email protected]>
* nv50: add remaining RGBX formatsChristoph Bumiller2013-04-181-4/+12
| | | | | | | | Not all are supported as render targets. The state tracker fallback of using RGBA instead of RGBX currently fails for blending, we could work around this by clearing their alpha to 1 and modifying the color mask to disable writing alpha.
* st/mesa: optionally apply texture swizzle to border color v2Christoph Bumiller2013-04-181-0/+2
| | | | | | | | | | | | This is the only sane solution for nv50 and nvc0 (really, trust me), but since on other hardware the border colour is tightly coupled with texture state they'd have to undo the swizzle, so I've added a cap. The dependency of update_sampler on the texture updates was introduced to avoid doing the apply_depthmode to the swizzle twice. v2: Moved swizzling helper to u_format.c, extended the CAP to provide more accurate information.
* nv50: set BORDER_COLOR_SRGB in sampler objectsChristoph Bumiller2013-04-182-19/+35
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* nv50: fix 4th component of Lx_SINT/UINT formatsChristoph Bumiller2013-04-181-6/+6
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* gallium: Disambiguate TGSI_OPCODE_IF.José Fonseca2013-04-172-2/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | TGSI_OPCODE_IF condition had two possible interpretations: - src.x != 0.0f - Mesa statetracker when PIPE_SHADER_CAP_INTEGERS was false either for vertex and fragment shaders - gallivm/llvmpipe - postprocess - vl state tracker - vega state tracker - most old drivers - old internal state trackers - many graw examples - src.x != 0U - Mesa statetracker when PIPE_SHADER_CAP_INTEGERS was true for both vertex and fragment shaders - tgsi_exec/softpipe - r600 - radeonsi - nv50 And drivers that use draw module also were a mess (because Mesa would emit float IFs, but draw module supports native integers so it would interpret IF arg as integers...) This sort of works if the source argument is limited to float +0.0f or +1.0f, integer 0, but would fail if source is float -0.0f, or integer in the float NaN range. It could also fail if source is integer 1, and hardware flushes denormalized numbers to zero. But with this change there are now two opcodes, IF and UIF, with clear meaning. Drivers that do not support native integers do not need to worry about UIF. However, for backwards compatibility with old state trackers and examples, it is advisable that native integer capable drivers also support the float IF opcode. I tried to implement this for r600 and radeonsi based on the surrounding code. I couldn't do this for nouveau, so I just shunted IF/UIF together, which matches the current behavior. Reviewed-by: Roland Scheidegger <[email protected]> Reviewed-by: Marek Olšák <[email protected]> v2: - Incorporate Roland's feedback. - Fix r600_shader.c merge conflict. - Fix typo in radeon, spotted by Michel Dänzer. - Incorporte Christoph Bumiller's patch to handle TGSI_OPCODE_IF(float) properly in nv50/ir.
* nv50/codegen: do not emitATOM() if the subOp is unknownEmil Velikov2013-04-121-1/+1
| | | | | | | | | | | | For debug build we'll hit the assert, for release we are going to emit random data as subOp is used uninitilised. Spotted by gcc codegen/nv50_ir_emit_nv50.cpp: In member function 'void nv50_ir::CodeEmitterNV50::emitATOM(const nv50_ir::Instruction*)': codegen/nv50_ir_emit_nv50.cpp:1554:12: warning: 'subOp' may be used uninitialized in this function [-Wmaybe-uninitialized] uint8_t subOp; ^ Signed-off-by: Emil Velikov <[email protected]>
* nvc0: implement multisample texturesChristoph Bumiller2013-04-124-6/+24
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* nv50,nvc0: add RGBX16/32_FLOAT formatsChristoph Bumiller2013-04-121-0/+4
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* nv50,nvc0: remove MS resolve formats hackChristoph Bumiller2013-04-031-5/+0
| | | | Mesa now allows BlitFramebuffer resolve between RGBA and BGRA.
* nvc0: place staging textures in GART and map them directlyChristoph Bumiller2013-04-032-4/+4
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* nv50: account for pesky prefetch in size calculation of linear texturesChristoph Bumiller2013-04-031-1/+6
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* nvc0: fix for 2d engine R source formats writing RRR1 and not R001Christoph Bumiller2013-04-032-24/+87
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* nv50,nvc0: disable DEPTH_RANGE_NEAR/FAR clipping during blitChristoph Bumiller2013-04-031-0/+2
| | | | | We send position.z == 0, DEPTH_RANGE may be some arbitrary range not including 0 (for exmaple in piglit's hiz tests).
* nouveau: accelerate buffer copies in resource_copy_regionChristoph Bumiller2013-04-031-3/+3
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* nvc0: add some driver statistics queriesChristoph Bumiller2013-04-031-0/+4
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* gallium: add PIPE_CAP_QUERY_PIPELINE_STATISTICSChristoph Bumiller2013-04-031-0/+2
| | | | Reviewed-by: Marek Olšák <[email protected]>
* nv50,nvc0: fix 3d blits, restore viewport after blitChristoph Bumiller2013-03-291-2/+6
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* nv50: fix 3D render target setupChristoph Bumiller2013-03-291-2/+10
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* gallium,st/mesa: don't use blit-based transfers with software rasterizersMarek Olšák2013-03-231-0/+2
| | | | | | | | | The blit-based paths for TexImage, GetTexImage, and ReadPixels aren't very fast with software rasterizer. Now Gallium drivers have the ability to turn them off. Reviewed-by: Brian Paul <[email protected]> Tested-by: Brian Paul <[email protected]>
* nvc0: fix max varying count, move CLIPVERTEX,FOG out of the wayChristoph Bumiller2013-03-201-5/+18
| | | | | | The card spews an error if I use all 128 generic slots. Apparently the real limit isn't just dictated by the address space layout.
* gallium: add TGSI_SEMANTIC_TEXCOORD,PCOORD v3Christoph Bumiller2013-03-203-5/+3
| | | | | | | | | | | | | | | This makes it possible to identify gl_TexCoord and gl_PointCoord for drivers where sprite coordinate replacement is restricted. The new PIPE_CAP_TGSI_TEXCOORD decides whether these varyings should be hidden behind the GENERIC semantic or not. With this patch only nvc0 and nv30 will request that they be used. v2: introduce a CAP so other drivers don't have to bother with the new semantic v3: adapt to introduction gl_varying_slot enum
* tgsi: use separate structure for indirect address v2Christian König2013-03-191-0/+6
| | | | | | | | | | | | | | To further improve the optimization of source and destination indirect addressing we need the ability to store a reference to the declaration of the addressed operands. Since most of the fields in tgsi_src_register doesn't apply for an indirect addressing operand replace it with a separate tgsi_ind_register structure and so make room for extra information. v2: rename Declaration to ArrayID, put the ArrayID into () instead of [] Signed-off-by: Christian König <[email protected]>
* tgsi: remove TGSI_FILE_(IMMEDIATE|TEMP)_ARRAYChristian König2013-03-191-80/+0
| | | | | | Nobody seems to be using it, and only nv50 had a partial implementation. Signed-off-by: Christian König <[email protected]>
* nvc0: they removed the NTID,NCTAID,GRIDID registers on nve4Christoph Bumiller2013-03-121-0/+1
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* nvc0: implement compute support for nve4Christoph Bumiller2013-03-121-7/+53
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* nv50/ir: add CCTL (cache control) opChristoph Bumiller2013-03-124-4/+8
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* nvc0: add SHADER/COMPUTE_RESOURCE bind flags to format tableChristoph Bumiller2013-03-121-43/+53
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* nv50,nvc0: copy writable flag on surface creationChristoph Bumiller2013-03-122-0/+2
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* nv50/ir: add support for different sampler and resource index on nve4Christoph Bumiller2013-03-122-0/+29
| | | | | | | | | | And remove non-working code for indirect sampler/resource selection. Will be added back later. Includes code from "nv50/ir/tgsi: Resource indirect indexing" by Francisco Jerez (when mixing the R and S handles we can only specify them via a register, i.e. indirectly, unless we upload all the used handle combinations to c[] space, which we don't for now).
* nv50/ir: implement splitting of 64 bit ops after RAChristoph Bumiller2013-03-125-20/+86
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* nv50/ir: fix size adjustment for sched info for multiple functionsChristoph Bumiller2013-03-121-6/+11
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* nv50/ir: print function inputs and outputsChristoph Bumiller2013-03-121-1/+22
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* nv50/ir/ssa: add a few comments regarding RenamePassChristoph Bumiller2013-03-121-0/+19
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* nv50/ir/tgsi: Exclude local declarations from function prototypes.Francisco Jerez2013-03-121-5/+28
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* nv50/ir/opt: try to make use of SUCLAMP addendChristoph Bumiller2013-03-121-0/+45
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* nv50/ir: don't assert on type in Modifier.applyTo if it is 0Christoph Bumiller2013-03-121-0/+2
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* nv50/ir: add support for barriersChristoph Bumiller2013-03-126-15/+65
| | | | nv50 part by Francisco Jerez.
* nv50/ir/tgsi: add support for atomicsChristoph Bumiller2013-03-121-0/+89
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* nv50/ir/tgsi: handle TGSI_OPCODE_LOAD,STOREChristoph Bumiller2013-03-127-30/+303
| | | | | | | | | | | | | | | | Squashed and (heavily) modified original patches by Francisco Jerez: nv50/ir/tgsi: Implement resource LOAD/STORE (wip). nv50/ir/tgsi: Emit SUST/SULD for surface access, and add CB LOAD/STORE support nv50/ir/tgsi: Fix/clean up the LOAD/STORE handling code. Left out for now: nv50/ir/tgsi: Resource indirect indexing Treating raw, read-only surfaces as constant buffers (CBs) was removed because CBs are limited to a size of 64 KiB which isn't desireable, and because this decision should probably be made by the state tracker. If we used a number of CB slots for surfaces, it might find that we cannot accomodate the advertised limit.
* nvc0/ir: implement lowering of surface ops for nve4Christoph Bumiller2013-03-126-13/+30
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* nv50/ir: extend moveSources for delta < 0Christoph Bumiller2013-03-122-16/+31
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* nv50/ir/emit: handle OP_ATOMChristoph Bumiller2013-03-121-0/+41
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* nv50/ir/opt: CALLs cannot loadChristoph Bumiller2013-03-121-0/+3
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* nv50/ir: add support for indirect BRA,CALLChristoph Bumiller2013-03-124-4/+12
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* nv50/ir: initialize CodeEmitters' specialized target fieldsChristoph Bumiller2013-03-121-3/+4
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* nv50/ir/opt: make optimization aware of atomics, barriers, surface opsChristoph Bumiller2013-03-122-1/+28
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* nv50/ir: add various new OPs that will be needed for computeChristoph Bumiller2013-03-128-45/+175
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