| Commit message (Collapse) | Author | Age | Files | Lines |
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Signed-off-by: Francisco Jerez <[email protected]>
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Changes in v3:
- Renumber caps to accomodate caps to add to master in the meantime
- Document caps
- Add unsupported caps to *_screen.c too
Changes in v2:
- Split for properties patch
- Use positive caps instead of negative caps
This adds 4 caps to indicate support of each of the fragment coord
conventions.
All drivers are also modifed to add the appropriate caps.
Some drivers were incorrectly using non-Gallium-default conventions,
and caps for them have them set so that they will behave correctly
after the later state tracker patches.
This drivers are softpipe/llvmpipe (uses integer rather than half
integer) and pre-nv50 Nouveau (uses lower left rather than upper left).
Other drivers might be broken. With this patchset, fixing them is
only a matter of exposing the appropriate caps that match the behavior
of the existing code.
Drivers are encouraged to support all conventions themselves for better
performance, and this feature is added to softpipe in a later patch.
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Conflicts:
src/gallium/drivers/softpipe/sp_screen.c
src/gallium/include/pipe/p_defines.h
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some drivers will complain if they don't know the cap bit
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"unsafe" is never initialized, but used
(found by valgrind)
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nv50_pre_pipebuffer_map references screen->cur_ctx which points
to freed memory after the context is destroyed.
This crash is easily triggerable by progs/xdemos/glxcontexts.
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Still not handling queries on multiple contexts though.
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This function was untested, sorry.
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And fix some obvious mistakes introduced in the
previous instancing commit.
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Fixes lockup triggered by this ingenious shader:
1: CALL :3
2: END
3: BGNSUB ...
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Too bad we don't have hw array divisors or a method for
setting startInstance.
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Vertex data in geometry programs is located in p[] space.
The base address in p[] for vertex i is located in vertex
attribute space, i.e. a[i << 2].
This means p[] is always accessed with an address register,
and I had to to mess with their allocation once again.
Also fixes negative offsets e.g. CONST[ADDR[0].x - 3].
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Conflicts:
src/gallium/drivers/softpipe/sp_draw_arrays.c
src/mesa/state_tracker/st_draw_feedback.c
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Conflicts:
src/mesa/drivers/dri/i965/brw_wm_emit.c
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NOUVEAU_BO_RD is defined (1 << 2), and `|' has higher precedence than `?'
so the second argument of nouveau_bo_map was always 0.
Signed-off-by: Roel Kluin <[email protected]>
Signed-off-by: Brian Paul <[email protected]>
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Otherwise we risk overwriting them with temporary GPRs if
they're not used immediately after the CALL.
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This patch removes PIPE_TEX_FILTER_ANISO.
Anisotropic filtering is enabled if and only if max_anisotropy > 1.0.
Values between 0.0 and 1.0, inclusive, of max_anisotropy are to be
considered equivalent, and meaning to turn off anisotropic filtering.
This approach has the small drawback of eliminating the possibility of
enabling anisotropic filter on either minification or magnification
separately, which Radeon hardware seems to support, is currently
support by Gallium but not exposed to OpenGL. If this is actually
useful it could be handled by splitting max_anisotropy in two values
and adding an appropriate OpenGL extension.
NOTE: some fiddling & reformatting by keithw to get this patch to
apply. Hopefully nothing broken in the process.
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- The previous solution was hacky and didn't do subchannel autobinding.
- The beheaviour should match what libdrm_nouveau does closely.
- The solution remains statically sized, but when debugging is on it will check
for abuse.
Signed-off-by: Maarten Maathuis <[email protected]>
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- This avoids problematic "reloc'ed while mapped" messages and
some associated corruption as well.
Signed-off-by: Maarten Maathuis <[email protected]>
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Conflicts:
src/gallium/drivers/identity/id_context.c
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The immediate's bits eat the condition bits.
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Cannot change hw reg assigned to a TGSI TEMP on the fly if
we are in a loop, conditional, or can jump around wildly.
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Not that they make much sense on nv50, but we also do LIT ...
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If we create multiple instances of an nv50_reg referencing
them same resource, register allocation from alloc_reg has
to be done with the original nv50_reg.
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