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* nvc0: do upload-time fixups for interpolation parametersIlia Mirkin2015-10-2915-19/+239
| | | | | | | | | | | | | | | | | Unfortunately flatshading is an all-or-nothing proposition on nvc0, while GL 3.0 calls for the ability to selectively specify explicit interpolation parameters on gl_Color/gl_SecondaryColor which would override the flatshading setting. This allows us to fix up the interpolation settings after shader generation based on rasterizer settings. While we're at it, we can add support for dynamically forcing all (non-flat) shader inputs to be interpolated per-sample, which allows st/mesa to not generate variants for these. Fixes the remaining failing glsl-1.30/execution/interpolation piglits. Signed-off-by: Ilia Mirkin <[email protected]>
* nv50: add ARB_copy_image supportIlia Mirkin2015-10-282-7/+11
| | | | Signed-off-by: Ilia Mirkin <[email protected]>
* nvc0: add ARB_copy_image supportIlia Mirkin2015-10-282-7/+11
| | | | Signed-off-by: Ilia Mirkin <[email protected]>
* nvc0: fix crash when nv50_miptree_from_handle failsJulien Isorce2015-10-281-1/+2
| | | | | Signed-off-by: Julien Isorce <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]>
* gallium: add PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATSMarek Olšák2015-10-283-0/+3
| | | | | | For ARB_copy_image. Reviewed-by: Brian Paul <[email protected]>
* nvc0: respect edgeflag attribute widthIlia Mirkin2015-10-231-7/+33
| | | | | | | | | | | | The edgeflag comes in as ubyte with glEdgeFlagPointer but as float with plain immediate glEdgeFlag. Avoid reading bytes that weren't meant for the edgeflag in the pointer case. Fixes intermittent failures with gl-2.0-edgeflag piglit (and valgrind complaints about reading uninitialized memory). Signed-off-by: Ilia Mirkin <[email protected]> Cc: [email protected]
* gallium: add PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINTMarek Olšák2015-10-203-0/+8
| | | | | | | | | | | | | | This avoids a serious r600g bug leading to a GPU hang. The chances this bug will get fixed are pretty low now. I deeply regret listening to others and not pushing this patch, leaving other users with a GPU-crashing driver. Yes, it should be fixed in the compiler and it's ugly, but users couldn't care less about that. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=86720 Cc: 11.0 10.6 <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* gallium: add PIPE_CAP_SHAREABLE_SHADERSMarek Olšák2015-10-203-0/+3
| | | | | | I'll let drivers figure out how to do it. Reviewed-by: Ilia Mirkin <[email protected]>
* nvc0: do not bind input params at compute state init on FermiSamuel Pitoiset2015-10-181-8/+0
| | | | | | | | | | | | | | | | | | It looks like binding a constant buffer on compute overwrites the 3D state. To avoid that, we already re-bind all the 3D constant buffers after launching a compute grid but this is not enough. Binding the constant buffer of input parameters for the compute state at initialization corrupts the 3D constant buffers, and it's just useless to bind it because this is not needed until we really launch a grid. This fixes some piglit regressions related to interpolation tests introduced in "nvc0: enable compute support by default on Fermi". Fixes: 00d6186 (nvc0: enable compute support by default on Fermi) Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* nvc0: add support for performance monitoring metrics on FermiSamuel Pitoiset2015-10-174-3/+500
| | | | | | | | | As explained in the CUDA toolkit documentation, "a metric is a characteristic of an application that is calculated from one or more event values." Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* nvc0: add a note about MP counters on GF100/GF110Samuel Pitoiset2015-10-161-0/+5
| | | | | | | | | MP counters on GF100/GF110 (compute capability 2.0) are buggy because there is a context-switch problem that we need to fix. Results might be wrong sometimes, be careful! Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* nvc0: add MP counters variants for GF100/GF110Samuel Pitoiset2015-10-162-77/+483
| | | | | | | | | GF100 and GF110 chipsets are compute capability 2.0, while the other Fermi chipsets are compute capability 2.1. That's why, some MP counters are different between these chipsets and we need to handle variants. Signed-off-by: Samuel Pitoiet <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* nvc0: move SW/HW queries info to their respective filesSamuel Pitoiset2015-10-167-178/+228
| | | | | | | This will help for handling HW SM queries variants on Fermi. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* nvc0: enable compute support by default on FermiSamuel Pitoiset2015-10-162-8/+2
| | | | | | | | | | Compute support was not enabled by default because weird effects on 3D state happened, but I can't reproduce them anymore. This also enables MP performance counters by default on Fermi. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* nvc0: allow only one active query for the MP counters groupSamuel Pitoiset2015-10-161-11/+9
| | | | | | | | | | | | | | Because we can't expose the number of hardware counters needed for each different query, we don't want to allow more than one active query simultaneously to avoid failure when the maximum number of counters is reached. Note that these groups of GPU counters are currently only used by AMD_performance_monitor. Like for Kepler, this limits the maximum number of active queries to 1 on Fermi. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* nvc0: read MP counters of all GPCs on FermiSamuel Pitoiset2015-10-161-1/+1
| | | | | | | | | | | | When a card has more than one GPC, the grid used by the compute kernel which reads MP performance counters seems to be too small. The consequence is that the kernel is not launched on all TPCs. Increasing the grid size using the number of GPCs now launches enough blocks and we can read MP performance counters of all TPCs. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* nvc0: store the number of GPCs to nvc0_screenSamuel Pitoiset2015-10-162-0/+2
| | | | | | | | | | | | NOUVEAU_GETPARAM_GRAPH_UNITS param returns the number of GPCs, the total number of TPCs and the number of ROP units. Note that when the DRM version is too old the default number of GPCs is fixed to 4. This will be used to launch the compute kernel which is used to read MP performance counters over all GPCs. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* nvc0: fix unaligned mem access when reading MP counters on FermiSamuel Pitoiset2015-10-161-6/+12
| | | | | | | | | | | | | Memory access have to be aligned to 128-bits. Note that this doesn't happen when the card only has TPC. This patch fixes the following dmesg fail: gr: GPC0/TPC1/MP trap: global 00000004 [MULTIPLE_WARP_ERRORS] warp 000f [UNALIGNED_MEM_ACCESS] Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* nvc0: fix monitoring multiple MP counters queries on FermiSamuel Pitoiset2015-10-161-76/+87
| | | | | | | | | For strange reasons, the signal id depends on the slot selected on Fermi but not on Kepler. Fortunately, the signal ids are just offseted by the slot id! Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* nvc0: fix queries which use multiple MP counters on FermiSamuel Pitoiset2015-10-161-47/+81
| | | | | | | | | | | | | | Queries which use more than one MP counters was misconfigured and computing the final result was also wrong because sources need to be configured on different hardware counters instead. According to the blob, computing the result is now as follows: FOR i..n val += ctr[i] * pow(2, i) Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* nvc0: allow to use 8 MP counters on FermiSamuel Pitoiset2015-10-162-19/+13
| | | | | | | | On Fermi, we have one domain of 8 MP counters while we have two domains of 4 MP counters on Kepler. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* nvc0: fix sequence field init for MP counters on FermiSamuel Pitoiset2015-10-161-2/+4
| | | | | | | | Sequence fields are located at MP[i] + 0x20 in the buffer object. This is used to check if result is available for MP[i]. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* nvc0: correctly enable the MP counters' multiplexer on FermiSamuel Pitoiset2015-10-161-4/+1
| | | | | | | | | Writing 0x408000 to 0x419e00 (like on Kepler) has no effect on Fermi because we only have one domain of 8 counters. Instead, we have to write 0x80000000. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* nvc0: rip off the kepler MP-enabling logic from the Fermi codepathSamuel Pitoiset2015-10-161-7/+1
| | | | | | | | Writing 0x1fcb to 0x419eac is definitely not related to MP counters and has no effect on Fermi (although this enables MP counters on Kepler). Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* nvc0: split out begin_query() hook used by MP countersSamuel Pitoiset2015-10-161-24/+84
| | | | | | | | | The way we configure MP performance counters is going to pretty different between Fermi and Kepler. Having two separate functions is much better. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* nvc0: remove useless call to query_get_cfg() in nvc0_hw_sm_query_end()Samuel Pitoiset2015-10-161-3/+1
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* nv30: include the header of ffs prototypeChih-Wei Huang2015-10-151-0/+1
| | | | | | | | It fixes a building error of the android 6.0 64-bit target. Signed-off-by: Chih-Wei Huang <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]> Cc: [email protected]
* nv50/ir: use C++11 standard std::unordered_map if possibleChih-Wei Huang2015-10-151-3/+17
| | | | | | | | Note Android version before Lollipop is not supported. Signed-off-by: Chih-Wei Huang <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]> Cc: [email protected]
* nouveau: avoid double-emitting fenceIlia Mirkin2015-10-121-1/+5
| | | | | | | | | | | The act of ensuring that there is space can cause a flush to happen, which will emit the current screen fence. If that is the fence we're trying to wait on, then it will have been emitted as a result of doing the PUSH_SPACE. Don't attempt to emit it a second time. Signed-off-by: Ilia Mirkin <[email protected]> Fixes: 8053c9208f (nouveau: avoid emitting new fences unnecessarily) Cc: [email protected]
* nv50,nvc0: don't base decisions on available pushbuf spaceIlia Mirkin2015-10-113-35/+10
| | | | | | | | | | | | We still have to push everything out, might as well kick earlier and flip pushbufs when we know we'll need it. This resolves some issues with the new policy of making sure that we always leave a bit of room at the end for fences. Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]> Fixes: 47d11990b (nouveau: make sure there's always room to emit a fence) Cc: [email protected]
* nouveau: avoid emitting new fences unnecessarilyIlia Mirkin2015-10-111-3/+9
| | | | | | | | | | | | | | | | | | | | Right now we emit on every kick, but this is only necessary if something will ever be able to observe that the fence completed. If there are no refs, leave the fence alone and emit it another day. This also happens to work around an issue for the kick handler -- a kick can be a result of e.g. nouveau_bo_wait or explicit kick, or it can be due to lack of space in the pushbuf. We want the emit to happen in the current batch, so we want there to always be enough space. However an explicit kick could take the reserved space for the implicitly-triggered kick's fence emission if it happened right after. With the new mechanism, hopefully there's no way to cause two fences to be emitted into the same reserved space. Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]> Fixes: 47d11990b (nouveau: make sure there's always room to emit a fence) Cc: [email protected]
* nvc0: make use of NVC0_COMPUTE_CLASS for GF110Samuel Pitoiset2015-10-101-5/+2
| | | | | | | | | | In theory, GF110+ should also support NVC8_COMPUTE_CLASS but, in practice, a ILLEGAL_CLASS dmesg fail appears when using it. This fixes compute support and MP performance counters on GF110. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* nvc0: move HW SM queries to nvc0_query_hw_sm.c/h filesSamuel Pitoiset2015-10-098-796/+908
| | | | | | | Global performance counters (PCOUNTER) will be added to nvc0_query_hw_pm.c/h files. Signed-off-by: Samuel Pitoiset <[email protected]>
* nvc0: move HW queries to nvc0_query_hw.c/h filesSamuel Pitoiset2015-10-098-1215/+1310
| | | | Signed-off-by: Samuel Pitoiset <[email protected]>
* nvc0: move SW queries to nvc0_query_sw.c/h filesSamuel Pitoiset2015-10-095-84/+204
| | | | | | Loosely based on freedreno driver. Signed-off-by: Samuel Pitoiset <[email protected]>
* nvc0: move nvc0_so_target_save_offset() to its correct locationSamuel Pitoiset2015-10-093-24/+19
| | | | Signed-off-by: Samuel Pitoiset <[email protected]>
* nvc0: add a header file for nvc0_querySamuel Pitoiset2015-10-097-189/+202
| | | | | | | | This will allow to split SW and HW queries in an upcoming patch. While we are at it, make use of nvc0_query struct instead of pipe_query. Signed-off-by: Samuel Pitoiset <[email protected]>
* nouveau: make sure there's always room to emit a fenceIlia Mirkin2015-10-074-2/+8
| | | | | | | | | | | | I started seeing a lot of situations on nv30 where fence emission wouldn't fit into the previous buffer (causing assertions). This ensures that whenever checking for space, we always leave a bit of extra room for the fence emission commands. Adjusts the nv30 and nvc0 fence emission logic to bypass the space checking as well. Signed-off-by: Ilia Mirkin <[email protected]> Cc: [email protected] Reviewed-by: Samuel Pitoiset <[email protected]>
* nv30: always go through translate module on big-endianIlia Mirkin2015-10-041-0/+4
| | | | | | | | | | It seems like things are either coming in slighly wrong, or perhaps uploaded incorrectly, but either way passing them through the translate module seems to fix everything. Eventually we should figure out what's going wrong and fix it "for real", but this should do for now. Signed-off-by: Ilia Mirkin <[email protected]> Cc: [email protected]
* nv30: pretend to have packed texture/surface formatsIlia Mirkin2015-10-041-12/+12
| | | | | | | | | This puts us in line with what the DDX/DRI2 st are expecting. It also happens to work... no idea why, but seems better to have it work than to ask lots of questions. Signed-off-by: Ilia Mirkin <[email protected]> Cc: [email protected]
* gallium: add per-sample interpolation control into rasterizer statOAeMarek Olšák2015-10-033-0/+3
| | | | | | | | Required by ARB_sample_shading for drivers that don't want a shader variant in st/mesa. Reviewed-by: Ilia Mirkin <[email protected]> Acked-by: Roland Scheidegger <[email protected]>
* nouveau: wait to unref the transfer's bo until it's no longer usedIlia Mirkin2015-09-281-2/+3
| | | | | | | | | | The bo will often come from a slab in which case it doesn't matter. But for larger allocations this will be in its own bo, and we have to make sure to wait until it's no longer used in order for it to be freed. Signed-off-by: Ilia Mirkin <[email protected]> Cc: [email protected] Tested-by: Marcin Ślusarz <[email protected]>
* nouveau: delay deleting buffer with unflushed fenceIlia Mirkin2015-09-282-2/+10
| | | | | | | | | | | If there is an unflushed fence on the bo, then the resource may still be used in commands built up in the local pushbuf. Flushing can cause all sorts of unwanted effects, so just free the bo when the relevant fence is hit. Signed-off-by: Ilia Mirkin <[email protected]> Cc: [email protected] Tested-by: Marcin Ślusarz <[email protected]>
* nouveau: be more careful about freeing temporary transfer buffersIlia Mirkin2015-09-285-4/+30
| | | | | | | | | Deleting a buffer does not flush the command stream. Make sure that we wait for the copies to finish before deleting the temporary bo. Signed-off-by: Ilia Mirkin <[email protected]> Cc: [email protected] Tested-by: Marcin Ślusarz <[email protected]>
* nv50,nvc0: flush texture cache in presence of coherent bufsIlia Mirkin2015-09-172-0/+39
| | | | | | | | This fixes the newly-added arb_texture_buffer_object-bufferstorage piglit test. Signed-off-by: Ilia Mirkin <[email protected]> Cc: "11.0" <[email protected]>
* nv50,nvc0: detect underlying resource changes and update ticIlia Mirkin2015-09-172-0/+43
| | | | | | | | | | | | | When updating texture buffers, we might end up replacing the whole buffer. Check that the tic address matches the resource address, and if not, update the tic and reupload it. This fixes: arb_direct_state_access-texture-buffer arb_texture_buffer_object-data-sync Signed-off-by: Ilia Mirkin <[email protected]> Cc: "11.0" <[email protected]>
* nv50, nvc0: fix max texture buffer size to 128M elementsIlia Mirkin2015-09-162-2/+2
| | | | | | | | This is what the hardware supports, there never was any sort of 64K limit. Signed-off-by: Ilia Mirkin <[email protected]> Cc: "10.6 11.0" <[email protected]>
* nvc0/ir: start offset at texBindBase for txq, like regular texturingIlia Mirkin2015-09-141-1/+4
| | | | | | | | | Curiously this has no actual effect. I think it's because the first 8 textures are bound in multiple slots for some reason. However seems prudent to use these the same way as regular texturing, esp in the case where there are more than 8 textures bound. Signed-off-by: Ilia Mirkin <[email protected]>
* nv50/ir: add support for TXQS tgsi opcodeIlia Mirkin2015-09-135-9/+41
| | | | Signed-off-by: Ilia Mirkin <[email protected]>
* gallium: add PIPE_CAP_TGSI_TXQS to let st know if TXQS is supportedIlia Mirkin2015-09-133-0/+3
| | | | | Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Glenn Kennard <[email protected]>
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