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* gallium: get rid of PIPE_CAP_SM3Erik Faye-Lund2019-07-103-3/+9
| | | | | | | | | | | | | | | | | | | | | PIPE_CAP_SM3 has always been an odd one out of all our caps. While most other caps are fine-grained and single-purpose, this cap encode several features in one. And since OpenGL cares more about single features, it'd be nice to get rid of this one. As it turns, this is now relatively simple. We only really care about three features using this cap, and those already got their own caps. So we can remove it, and make sure all current drivers just give the same response to all of them. The only place we *really* care about SM3 is in nine, and there we can instead just re-construct the information based on the finer-grained caps. This avoids DX9 semantics from needlessly leaking into all of the drivers, most of who doesn't care a whole lot about DX9 specifically. Signed-off-by: Erik Faye-Lund <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Acked-by: Alyssa Rosenzweig <[email protected]>
* nv50/ir/nir: implement load/store_globalKarol Herbst2019-07-101-0/+36
| | | | | | | | | required by OpenCL v2: fix setting globalAccess Signed-off-by: Karol Herbst <[email protected]> Reviewed-by: Pierre Moreau <[email protected]>
* nv50/ir/nir: handle kernel inputsKarol Herbst2019-07-101-3/+18
| | | | | | | required by OpenCL Signed-off-by: Karol Herbst <[email protected]> Reviewed-by: Pierre Moreau <[email protected]>
* nv50/ir/nir: don't assert on !mainKarol Herbst2019-07-101-2/+0
| | | | | | | required for OpenCL Signed-off-by: Karol Herbst <[email protected]> Reviewed-by: Pierre Moreau <[email protected]>
* nv50/ir/nir: parse system values first and stop for compute shadersKarol Herbst2019-07-101-29/+32
| | | | | | | required by OpenCL Signed-off-by: Karol Herbst <[email protected]> Reviewed-by: Pierre Moreau <[email protected]>
* nvc0: remove nvc0_program.tp.input_patch_sizeKarol Herbst2019-07-093-6/+0
| | | | | | | right now that's dead code Signed-off-by: Karol Herbst <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* nouveau: handle new CAPSKarol Herbst2019-07-022-0/+26
| | | | | Signed-off-by: Karol Herbst <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* nir: Add lower_rotate flag and set to true in all driversSagar Ghuge2019-07-011-0/+1
| | | | | | Signed-off-by: Sagar Ghuge <[email protected]> Suggested-by: Matt Turner <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* gallium: Add CAP for opcode DIVGert Wollny2019-06-303-0/+3
| | | | | | | | Not all drivers support TGSI_OPCODE_DIV, so we should have a cap to be able to check this. Signed-off-by: Gert Wollny <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* nir: remove fnot/fxor/fand/for opcodesJonathan Marek2019-06-261-8/+0
| | | | | | | | | | There doesn't seem to be any reason to keep these opcodes around: * fnot/fxor are not used at all. * fand/for are only used in lower_alu_to_scalar, but easily replaced Signed-off-by: Jonathan Marek <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* nir: define behavior of nir_op_bfm and nir_op_u/ibfe according to SM5 spec.Daniel Schürmann2019-06-241-1/+0
| | | | | | | | | | | That is: the five least significant bits provide the values of 'bits' and 'offset' which is the case for all hardware currently supported by NIR and using the bfm/bfe instructions. This patch also changes the lowering of bitfield_insert/extract using shifts to not use bfm and removes the flag 'lower_bfm'. Tested-by: Eric Anholt <[email protected]> Reviewed-by: Connor Abbott <[email protected]>
* nouveau: fix frees in unsupported IR error paths.Dave Airlie2019-06-194-0/+6
| | | | | | | | This is pointless in that we won't ever hit those paths in real life, but coverity complains. Fixes: f014ae3c7cce ("nouveau: add support for nir") Reviewed-by: Ilia Mirkin <[email protected]>
* u_dynarray: turn util_dynarray_{grow, resize} into element-oriented macrosNicolai Hähnle2019-06-123-7/+5
| | | | | | | | | | | | | | | | | | | | | | | | The main motivation for this change is API ergonomics: most operations on dynarrays are really on elements, not on bytes, so it's weird to have grow and resize as the odd operations out. The secondary motivation is memory safety. Users of the old byte-oriented functions would often multiply a number of elements with the element size, which could overflow, and checking for overflow is tedious. With this change, we only need to implement the overflow checks once. The checks are cheap: since eltsize is a compile-time constant and the functions should be inlined, they only add a single comparison and an unlikely branch. v2: - ensure operations are no-op when allocation fails - in util_dynarray_clone, call resize_bytes with a compile-time constant element size v3: - fix iris, lima, panfrost Reviewed-by: Marek Olšák <[email protected]>
* nir: Combine lower_fmod16/32 back into a single lower_fmod.Kenneth Graunke2019-06-051-1/+1
| | | | | | | | | | | | | | We originally had a single lower_fmod option. In commit 2ab2d2e5, Sam split 32 and 64-bit lowering into separate flags, with the rationale that some drivers might want different options there. This left 16-bit unhandled, so Iago added a lower_fmod16 option in commit ca31df6f. Now that lower_fmod64 is gone (in favor of nir_lower_doubles and nir_lower_dmod), we re-combine lower_fmod16 and lower_fmod32 into a single lower_fmod flag again. I'm not aware of any hardware which need lowering for one bitsize and not the other. Reviewed-by: Marek Olšák <[email protected]>
* nouveau: Use nir_lower_doubles instead of lower_fmod64 on nvc0.Kenneth Graunke2019-06-051-2/+1
| | | | | | | | | | We currently have two duplicate mechanisms for lowering fmod@64. One is a nir_opt_algebraic rule keyed off of options->lower_fmod64, and the other is nir_lower_doubles, which offers a full gamut of fp64 lowering. The latter works slightly better in some corner cases, so I'm trying to eliminate lower_fmod64 and drop the redundancy. Reviewed-by: Marek Olšák <[email protected]>
* gallium: Drop lower_fmod64 from drivers that don't support doubles.Kenneth Graunke2019-06-051-1/+0
| | | | | | | Neither freedreno nor nv50 expose PIPE_CAP_DOUBLES, so there's no fmod64 to be lowered. Reviewed-by: Marek Olšák <[email protected]>
* nir: Drop imov/fmov in favor of one mov instructionJason Ekstrand2019-05-241-2/+1
| | | | | | | | | | | | | | | | The difference between imov and fmov has been a constant source of confusion in NIR for years. No one really knows why we have two or when to use one vs. the other. The real reason is that they do different things in the presence of source and destination modifiers. However, without modifiers (which many back-ends don't have), they are identical. Now that we've reworked nir_lower_to_source_mods to leave one abs/neg instruction in place rather than replacing them with imov or fmov instructions, we don't need two different instructions at all anymore. Reviewed-by: Kristian H. Kristensen <[email protected]> Reviewed-by: Alyssa Rosenzweig <[email protected]> Reviewed-by: Vasily Khoruzhick <[email protected]> Acked-by: Rob Clark <[email protected]>
* gallium: Change PIPE_CAP_TGSI_FS_FBFETCH bool to PIPE_CAP_FBFETCH countKenneth Graunke2019-05-233-4/+4
| | | | | | | | | | | | | | TGSI's FBFETCH instruction currently only supports reading from a single render target, but NIR intrinsics can support multiple render targets. radeonsi can only support fetching from RT 0, but other drivers may be able to support fetching from any render target. To express this, this patch renames PIPE_CAP_TGSI_FS_FBFETCH to simply PIPE_CAP_FBFETCH, and converts it from a boolean "is FBFETCH supported?" to an integer number of render targets which can be fetched. Reviewed-by: Marek Olšák <[email protected]>
* nv50/ir/nir: make use of SYSTEM_VALUE_MAX when iterating read sysvalsKarol Herbst2019-05-131-1/+1
| | | | | Signed-off-by: Karol Herbst <[email protected]> Reviewed-by: Pierre Moreau <[email protected]>
* nv50/ir/nir: prefer to shift 1ull instead of 1llKarol Herbst2019-05-131-2/+2
| | | | | | Signed-off-by: Karol Herbst <[email protected]> Suggested-by: Ilia Mirkin <[email protected]> Reviewed-by: Pierre Moreau <[email protected]>
* gallium: Redefine the max texture 2d cap from _LEVELS to _SIZE.Eric Anholt2019-05-133-5/+6
| | | | | | | | The _LEVELS assumes that the max is always power of two. For V3D 4.2, we can support up to 7680 non-power-of-two MSAA textures, which will let X11 support dual 4k displays on newer hardware. Reviewed-by: Marek Olšák <[email protected]>
* nir: allow specifying a set of opcodes in lower_alu_to_scalarJonathan Marek2019-05-101-1/+1
| | | | | | | | | This can be used by both etnaviv and freedreno/a2xx as they are both vec4 architectures with some instructions being scalar-only. Signed-off-by: Jonathan Marek <[email protected]> Reviewed-by: Christian Gmeiner <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* nir: nir_shader_compiler_options: drop native_integersChristian Gmeiner2019-05-072-2/+0
| | | | | | | | Driver which do not support native integers should use a lowering pass to go from integers to floats. Signed-off-by: Christian Gmeiner <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* delete autotools .gitignore filesEric Engestrom2019-04-291-1/+0
| | | | | | | | One special case, `src/util/xmlpool/.gitignore` is not entirely deleted, as `xmlpool.pot` still gets generated (eg. by `ninja xmlpool-pot`). Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Dylan Baker <[email protected]>
* nouveau: support NULL-resourcesErik Faye-Lund2019-04-292-3/+10
| | | | | | | | It's legal for a buffer-object to have a NULL-resource, but let's just skip over it, as there's nothing to do. Signed-off-by: Erik Faye-Lund <[email protected]> Acked-by: Karol Herbst <[email protected]>
* gallium: set PIPE_CAP_MAX_FRAMES_IN_FLIGHT to 2 for all driversMarek Olšák2019-04-243-9/+0
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* gallium: replace DRM_CONF_THROTTLE with PIPE_CAP_MAX_FRAMES_IN_FLIGHTMarek Olšák2019-04-233-0/+9
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* Delete autotoolsDylan Baker2019-04-152-73/+0
| | | | | | | | | | Acked-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Eric Engestrom <[email protected]> Acked-by: Marek Olšák <[email protected]> Acked-by: Jason Ekstrand <[email protected]> Acked-by: Bas Nieuwenhuizen <[email protected]> Acked-by: Matt Turner <[email protected]>
* gallium: add support for formatted image loadsRhys Perry2019-04-153-0/+3
| | | | | | | | v3: rebase v3: make use of u_pipe_screen_get_param_defaults Signed-off-by: Rhys Perry <[email protected]> Signed-off-by: Marek Olšák <[email protected]>
* nir: make nir_const_value scalarKarol Herbst2019-04-141-5/+5
| | | | | | | | | v2: remove & operator in a couple of memsets add some memsets v3: fixup lima Signed-off-by: Karol Herbst <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> (v2)
* nvc0/nir: enable bindless textureKarol Herbst2019-04-121-1/+1
| | | | Signed-off-by: Karol Herbst <[email protected]>
* nv50/ir/nir: add support for bindless imagesKarol Herbst2019-04-121-4/+152
| | | | Signed-off-by: Karol Herbst <[email protected]>
* nv50/ir/nir: handle bindless textureKarol Herbst2019-04-121-2/+18
| | | | Signed-off-by: Karol Herbst <[email protected]>
* nir/i965/freedreno/vc4: add a bindless bool to type size functionsTimothy Arceri2019-04-121-2/+2
| | | | | | | This required to calculate sizes correctly when we have bindless samplers/images. Reviewed-by: Marek Olšák <[email protected]>
* gallium: add writable_bitmask parameter into set_shader_buffersMarek Olšák2019-04-041-1/+2
| | | | | | | to indicate write usage per buffer. This is just a hint (it will be used by radeonsi). Reviewed-by: Timothy Arceri <[email protected]>
* nv50/ir/nir: support gather offsetsKarol Herbst2019-03-212-3/+16
| | | | | | v2: only emit offsets if those are !0 Signed-off-by: Karol Herbst <[email protected]>
* nvc0: Skip new update barrier bitsKenneth Graunke2019-03-201-0/+3
| | | | | | | | | | | I added new barrier bits in 220c1dce1e3194ea867e6d948fc7ff5b9ef2d3a7 and made most drivers skip them. I thought nvc0 was already skipping those but missed the else case here, which does something. So make it explicitly skip like I did everywhere else. Thanks to Ilia for catching this. Fixes: 220c1dce1e3 gallium: Add PIPE_BARRIER_UPDATE_BUFFER and UPDATE_TEXTURE bits.
* android: nouveau: add support for nirMauro Rossi2019-03-181-1/+6
| | | | | | | | Add the necessary build rules for android, to avoid building errors. Fixes: f014ae3 ("nouveau: add support for nir") Signed-off-by: Mauro Rossi <[email protected]> Reviewed-by: Karol Herbst <[email protected]>
* nv50ir/nir: move immediates before useKarol Herbst2019-03-171-18/+41
| | | | Signed-off-by: Karol Herbst <[email protected]>
* nv50/ir/nir: handle user clip planes for each emitted vertexKarol Herbst2019-03-171-1/+7
| | | | | | | v9: convert to C++ style comments handle for tess eval shaders as well Signed-off-by: Karol Herbst <[email protected]>
* nv50/ir/nir: implement intrinsic shader_clockKarol Herbst2019-03-171-0/+8
| | | | | | v9: mark as fixed Signed-off-by: Karol Herbst <[email protected]>
* nv50/ir/nir: implement load_per_vertex_outputKarol Herbst2019-03-171-0/+23
| | | | | | | | | v4: use smarter getIndirect helper use new getSlotAddress helper v5: use loadFrom helper v8: don't require C++11 features Signed-off-by: Karol Herbst <[email protected]>
* nv50/ir/nir: add memory barriersKarol Herbst2019-03-171-0/+21
| | | | | | v5: add more barrier intrinsics Signed-off-by: Karol Herbst <[email protected]>
* nv50/ir/nir: implement imagesKarol Herbst2019-03-171-10/+380
| | | | | | | | | | | | | | | | | | | | v3: fix compiler warnings v4: use loadFrom helper v5: fix signed min/max v6: set tex mask add support for indirect image access set cache mode v7: make compatible with 884d27bcf688d36c3bbe01bceca525595add3b33 rework the whole deref thing to prepare for bindless v8: port to deref instructions don't require C++11 features v9: implement MS images rebase on master (image modifiers) fix regressions due to variable src compnents replace '(*it).' with 'it->' convert to C++ style comments Signed-off-by: Karol Herbst <[email protected]>
* nv50/ir/nir: implement ssbo intrinsicsKarol Herbst2019-03-171-0/+90
| | | | | | | | v4: use loadFrom helper v5: support indirect buffer access v8: don't require C++11 features Signed-off-by: Karol Herbst <[email protected]>
* nv50/ir/nir: implement nir_intrinsic_load_uboKarol Herbst2019-03-171-0/+14
| | | | | | | v4: use loadFrom helper v8: don't require C++11 features Signed-off-by: Karol Herbst <[email protected]>
* nv50/ir/nir: implement geometry shader nir_intrinsicsKarol Herbst2019-03-171-0/+27
| | | | | | | | | v4: use smarter getIndirect helper use new getSlotAddress helper use loadFrom helper v8: don't require C++11 features Signed-off-by: Karol Herbst <[email protected]>
* nv50/ir/nir: implement variable indexingKarol Herbst2019-03-171-0/+58
| | | | | | | | | | | | | | We store those arrays in local memory and reserve some space for each of the arrays. With NIR we could store those arrays packed, but we don't do that yet as it causes MemoryOpt to generate unaligned memory accesses. v3: use fixed size vec4 arrays until we fix MemoryOpt v4: fix for 64 bit types v5: use loadFrom helper v8: don't require C++11 features v9: convert to C++ style comments Signed-off-by: Karol Herbst <[email protected]>
* nv50/ir/nir: implement vote and ballotKarol Herbst2019-03-171-0/+48
| | | | | | | | | | | | | v2: add vote_eq support use the new subop intrinsic helper add ballot v3: add read_(first_)invocation v8: handle vectorized intrinsics don't require C++11 features v9: lower_subgroups to 32 bit (produces less instructions) use getSSA and getScratch instead of new_LValue Signed-off-by: Karol Herbst <[email protected]>
* nv50/ir/nir: add skeleton getOperation for intrinsicsKarol Herbst2019-03-171-0/+22
| | | | | | | v7: don't assert in default case for getSubOp Signed-off-by: Karol Herbst <[email protected]> Reviewed-by: Pierre Moreau <[email protected]>
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