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path: root/src/gallium/drivers/nouveau
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* nv50/ir: Split 64-bit integer MAD/MUL operationsPierre Moreau2017-02-091-0/+116
* nvc0/ir: add a "high" subop for shifts, emit shf.l/shf.r for 64-bitIlia Mirkin2017-02-093-3/+74
* nvc0/ir: fix SET and SLCT emissionIlia Mirkin2017-02-092-0/+6
* nvc0/ir: add support for emitting partial min/max ops for int64Ilia Mirkin2017-02-094-1/+14
* gallium: add separate PIPE_CAP_INT64_DIVMODIlia Mirkin2017-02-093-0/+3
* gallium: turn PIPE_SHADER_CAP_DOUBLES into a screen capabilityNicolai Hähnle2017-02-023-5/+3
* nouveau: remove explicit __STDC_FORMAT_MACROS defineEmil Velikov2017-01-271-1/+0
* gallium: Add integer 64 capabilityDave Airlie2017-01-273-0/+3
* nv50: add support for MUL_ZERO_WINS propertyIlia Mirkin2017-01-235-2/+11
* nvc0: add support for MUL_ZERO_WINS propertyIlia Mirkin2017-01-234-9/+25
* gallium: add PIPE_CAP_TGSI_MUL_ZERO_WINSIlia Mirkin2017-01-233-0/+3
* nouveau: remove always false argument in nouveau_fence_new()Emil Velikov2017-01-185-11/+6
* nv50/ir: optimize shl + andIlia Mirkin2017-01-161-0/+11
* nvc0: enable FBFETCH with a special slot for color buffer 0Ilia Mirkin2017-01-169-6/+172
* gallium: add flags parameter to texture barrierIlia Mirkin2017-01-162-2/+2
* gallium: add PIPE_CAP_TGSI_FS_FBFETCHIlia Mirkin2017-01-163-0/+3
* nvc0: true up exposing of the HW_METRIC_QUERY_GROUP for maxwellIlia Mirkin2017-01-161-2/+2
* nv50/ir: handle new DDIV op which will be used for double divisionsIlia Mirkin2017-01-161-0/+3
* nvc0/ir: emit FMZ flag when requested on FFMAIlia Mirkin2017-01-151-0/+4
* nvc0/ir: only try to check for zero LOD if we aren't already forcing itIlia Mirkin2017-01-121-1/+1
* nouveau: take extra push space into account for pushbuf_space callsIlia Mirkin2017-01-1215-56/+26
* nvc0: enable GL 4.3 on gm107+Samuel Pitoiset2017-01-121-7/+4
* nvc0: use sched control codes for gm107 MP counters codeSamuel Pitoiset2017-01-121-44/+44
* nvc0: use sched control codes for gm107 blitter shaderSamuel Pitoiset2017-01-121-6/+14
* nv50/ir: use sched control codes for gm107 builtinsSamuel Pitoiset2017-01-122-40/+40
* nv50/ir: improve instruction pipelining on gm107Samuel Pitoiset2017-01-123-4/+1027
* nv50/ir: do not insert texture barriers on gm107Samuel Pitoiset2017-01-121-1/+2
* gallium: remove TGSI_OPCODE_SUBMarek Olšák2017-01-053-8/+0
* gallium: remove TGSI_OPCODE_ABSMarek Olšák2017-01-053-9/+0
* gallium: add PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELYMarek Olšák2017-01-053-0/+3
* gallium: support for native fence fd'sRob Clark2016-12-013-0/+3
* gallium: add PIPE_CAP_TGSI_CAN_READ_OUTPUTSNicolai Hähnle2016-11-303-0/+3
* gm107/ir: optimize 32-bit CONST load to movSamuel Pitoiset2016-11-262-0/+17
* gm107/ir: do not combine CONST loadsSamuel Pitoiset2016-11-261-2/+7
* nvc0/ir: use levelZero flag when the lod is set to 0Ilia Mirkin2016-11-202-6/+43
* gallium: add PIPE_SHADER_CAP_LOWER_IF_THRESHOLDMarek Olšák2016-11-153-0/+4
* nvc0: support MP performance counters on MaxwellSamuel Pitoiset2016-11-103-3/+721
* nvc0: simplify draw parameters upload for vertex shadersSamuel Pitoiset2016-11-071-8/+6
* nvc0: get rid of NVE4_COMPUTE_MP_PM_{A,B}_SIGSEL_XXXSamuel Pitoiset2016-11-051-56/+56
* gm107/ir: emit RED instead of ATOM when no dstSamuel Pitoiset2016-11-051-1/+28
* nv50,nvc0: stop limiting the number of active queries to 1Samuel Pitoiset2016-11-022-16/+12
* nvc0: add new warp_nonpred_execution_efficiency metric on SM35Samuel Pitoiset2016-11-022-1/+37
* nvc0: add missing metric-issue_slot on SM35Samuel Pitoiset2016-11-021-0/+1
* nvc0: do not expose metric-inst_issued twice on SM35Samuel Pitoiset2016-11-021-1/+0
* nvc0: add new warp_execution_efficiency metric on SM30+Samuel Pitoiset2016-11-022-0/+24
* nvc0: respect 80-chars for perf metrics descriptionsSamuel Pitoiset2016-11-021-4/+4
* nvc0: sort performance metrics alphabeticallySamuel Pitoiset2016-11-021-4/+4
* nv50: add missing draw_calls_indexed driver statSamuel Pitoiset2016-11-021-0/+1
* nvc0: do not duplicate similar performance metricsSamuel Pitoiset2016-11-011-43/+7
* nvc0/ir: fix emission of IMAD with NEG modifiersSamuel Pitoiset2016-10-272-2/+2
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