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* nvc0: respect edgeflag attribute widthIlia Mirkin2015-10-231-7/+33
* gallium: add PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINTMarek Olšák2015-10-203-0/+8
* gallium: add PIPE_CAP_SHAREABLE_SHADERSMarek Olšák2015-10-203-0/+3
* nvc0: do not bind input params at compute state init on FermiSamuel Pitoiset2015-10-181-8/+0
* nvc0: add support for performance monitoring metrics on FermiSamuel Pitoiset2015-10-174-3/+500
* nvc0: add a note about MP counters on GF100/GF110Samuel Pitoiset2015-10-161-0/+5
* nvc0: add MP counters variants for GF100/GF110Samuel Pitoiset2015-10-162-77/+483
* nvc0: move SW/HW queries info to their respective filesSamuel Pitoiset2015-10-167-178/+228
* nvc0: enable compute support by default on FermiSamuel Pitoiset2015-10-162-8/+2
* nvc0: allow only one active query for the MP counters groupSamuel Pitoiset2015-10-161-11/+9
* nvc0: read MP counters of all GPCs on FermiSamuel Pitoiset2015-10-161-1/+1
* nvc0: store the number of GPCs to nvc0_screenSamuel Pitoiset2015-10-162-0/+2
* nvc0: fix unaligned mem access when reading MP counters on FermiSamuel Pitoiset2015-10-161-6/+12
* nvc0: fix monitoring multiple MP counters queries on FermiSamuel Pitoiset2015-10-161-76/+87
* nvc0: fix queries which use multiple MP counters on FermiSamuel Pitoiset2015-10-161-47/+81
* nvc0: allow to use 8 MP counters on FermiSamuel Pitoiset2015-10-162-19/+13
* nvc0: fix sequence field init for MP counters on FermiSamuel Pitoiset2015-10-161-2/+4
* nvc0: correctly enable the MP counters' multiplexer on FermiSamuel Pitoiset2015-10-161-4/+1
* nvc0: rip off the kepler MP-enabling logic from the Fermi codepathSamuel Pitoiset2015-10-161-7/+1
* nvc0: split out begin_query() hook used by MP countersSamuel Pitoiset2015-10-161-24/+84
* nvc0: remove useless call to query_get_cfg() in nvc0_hw_sm_query_end()Samuel Pitoiset2015-10-161-3/+1
* nv30: include the header of ffs prototypeChih-Wei Huang2015-10-151-0/+1
* nv50/ir: use C++11 standard std::unordered_map if possibleChih-Wei Huang2015-10-151-3/+17
* nouveau: avoid double-emitting fenceIlia Mirkin2015-10-121-1/+5
* nv50,nvc0: don't base decisions on available pushbuf spaceIlia Mirkin2015-10-113-35/+10
* nouveau: avoid emitting new fences unnecessarilyIlia Mirkin2015-10-111-3/+9
* nvc0: make use of NVC0_COMPUTE_CLASS for GF110Samuel Pitoiset2015-10-101-5/+2
* nvc0: move HW SM queries to nvc0_query_hw_sm.c/h filesSamuel Pitoiset2015-10-098-796/+908
* nvc0: move HW queries to nvc0_query_hw.c/h filesSamuel Pitoiset2015-10-098-1215/+1310
* nvc0: move SW queries to nvc0_query_sw.c/h filesSamuel Pitoiset2015-10-095-84/+204
* nvc0: move nvc0_so_target_save_offset() to its correct locationSamuel Pitoiset2015-10-093-24/+19
* nvc0: add a header file for nvc0_querySamuel Pitoiset2015-10-097-189/+202
* nouveau: make sure there's always room to emit a fenceIlia Mirkin2015-10-074-2/+8
* nv30: always go through translate module on big-endianIlia Mirkin2015-10-041-0/+4
* nv30: pretend to have packed texture/surface formatsIlia Mirkin2015-10-041-12/+12
* gallium: add per-sample interpolation control into rasterizer statOAeMarek Olšák2015-10-033-0/+3
* nouveau: wait to unref the transfer's bo until it's no longer usedIlia Mirkin2015-09-281-2/+3
* nouveau: delay deleting buffer with unflushed fenceIlia Mirkin2015-09-282-2/+10
* nouveau: be more careful about freeing temporary transfer buffersIlia Mirkin2015-09-285-4/+30
* nv50,nvc0: flush texture cache in presence of coherent bufsIlia Mirkin2015-09-172-0/+39
* nv50,nvc0: detect underlying resource changes and update ticIlia Mirkin2015-09-172-0/+43
* nv50, nvc0: fix max texture buffer size to 128M elementsIlia Mirkin2015-09-162-2/+2
* nvc0/ir: start offset at texBindBase for txq, like regular texturingIlia Mirkin2015-09-141-1/+4
* nv50/ir: add support for TXQS tgsi opcodeIlia Mirkin2015-09-135-9/+41
* gallium: add PIPE_CAP_TGSI_TXQS to let st know if TXQS is supportedIlia Mirkin2015-09-133-0/+3
* nv50/ir: don't fold immediate into mad if registers are too highIlia Mirkin2015-09-101-0/+4
* nv50/ir: fix emission of 8-byte wide interp instructionIlia Mirkin2015-09-101-5/+6
* nv50/ir: r63 is only 0 if we are using less than 63 registersIlia Mirkin2015-09-101-1/+4
* nv50/ir: make edge splitting fix up phi node sourcesIlia Mirkin2015-09-101-13/+77
* nvc0: remove BGRA4 format supportIlia Mirkin2015-09-091-0/+2
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