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* nouveau: avoid double-emitting fenceIlia Mirkin2015-10-121-1/+5
* nv50,nvc0: don't base decisions on available pushbuf spaceIlia Mirkin2015-10-113-35/+10
* nouveau: avoid emitting new fences unnecessarilyIlia Mirkin2015-10-111-3/+9
* nvc0: make use of NVC0_COMPUTE_CLASS for GF110Samuel Pitoiset2015-10-101-5/+2
* nvc0: move HW SM queries to nvc0_query_hw_sm.c/h filesSamuel Pitoiset2015-10-098-796/+908
* nvc0: move HW queries to nvc0_query_hw.c/h filesSamuel Pitoiset2015-10-098-1215/+1310
* nvc0: move SW queries to nvc0_query_sw.c/h filesSamuel Pitoiset2015-10-095-84/+204
* nvc0: move nvc0_so_target_save_offset() to its correct locationSamuel Pitoiset2015-10-093-24/+19
* nvc0: add a header file for nvc0_querySamuel Pitoiset2015-10-097-189/+202
* nouveau: make sure there's always room to emit a fenceIlia Mirkin2015-10-074-2/+8
* nv30: always go through translate module on big-endianIlia Mirkin2015-10-041-0/+4
* nv30: pretend to have packed texture/surface formatsIlia Mirkin2015-10-041-12/+12
* gallium: add per-sample interpolation control into rasterizer statOAeMarek Olšák2015-10-033-0/+3
* nouveau: wait to unref the transfer's bo until it's no longer usedIlia Mirkin2015-09-281-2/+3
* nouveau: delay deleting buffer with unflushed fenceIlia Mirkin2015-09-282-2/+10
* nouveau: be more careful about freeing temporary transfer buffersIlia Mirkin2015-09-285-4/+30
* nv50,nvc0: flush texture cache in presence of coherent bufsIlia Mirkin2015-09-172-0/+39
* nv50,nvc0: detect underlying resource changes and update ticIlia Mirkin2015-09-172-0/+43
* nv50, nvc0: fix max texture buffer size to 128M elementsIlia Mirkin2015-09-162-2/+2
* nvc0/ir: start offset at texBindBase for txq, like regular texturingIlia Mirkin2015-09-141-1/+4
* nv50/ir: add support for TXQS tgsi opcodeIlia Mirkin2015-09-135-9/+41
* gallium: add PIPE_CAP_TGSI_TXQS to let st know if TXQS is supportedIlia Mirkin2015-09-133-0/+3
* nv50/ir: don't fold immediate into mad if registers are too highIlia Mirkin2015-09-101-0/+4
* nv50/ir: fix emission of 8-byte wide interp instructionIlia Mirkin2015-09-101-5/+6
* nv50/ir: r63 is only 0 if we are using less than 63 registersIlia Mirkin2015-09-101-1/+4
* nv50/ir: make edge splitting fix up phi node sourcesIlia Mirkin2015-09-101-13/+77
* nvc0: remove BGRA4 format supportIlia Mirkin2015-09-091-0/+2
* nvc0: keep track of cb bindings per buffer, use for upload settingsIlia Mirkin2015-09-097-12/+58
* nv30: Disable msaa unless requested from the env by NV30_MAX_MSAAHans de Goede2015-09-092-1/+21
* nv30: Fix color resolving for nv3x cardsHans de Goede2015-09-091-1/+37
* nouveau: android: add space before PRIx64 macroMauro Rossi2015-09-091-1/+1
* nvc0: always emit a full shader colormaskIlia Mirkin2015-09-081-1/+1
* nv30: Fix max width / height checks in nv30 sifm codeHans de Goede2015-09-071-2/+2
* nouveau: don't mark full range as used on unmap with explicit flushIlia Mirkin2015-09-051-5/+7
* nv50: avoid using inline vertex data submit when gl_VertexID is usedIlia Mirkin2015-09-054-2/+14
* nv50: don't flush vertex arrays when index buffer changesIlia Mirkin2015-09-051-4/+0
* nv50: rebind bo to bufctx when invalidating idxbuf storageIlia Mirkin2015-09-051-1/+5
* nv50: clear buffer status on all vertex bufs, not just the first oneIlia Mirkin2015-09-051-1/+0
* nv50: fix drawing from tfb, direct-to-pushbuf submitsIlia Mirkin2015-09-054-14/+15
* nv30: Implement color resolve for msaaHans de Goede2015-09-042-14/+8
* nv30: Fix creation of scanout buffersHans de Goede2015-09-041-0/+10
* nvc0: change prefix of MP performance counters to HW_SMSamuel Pitoiset2015-08-292-149/+149
* nvc0: sort performance counter queries by nameSamuel Pitoiset2015-08-292-142/+142
* nvc0: make names of performance counter queries consistentSamuel Pitoiset2015-08-292-56/+56
* nvc0: use enumerations for driver queriesSamuel Pitoiset2015-08-291-120/+123
* nvc0: remove commented out code related to PCOUNTER queriesSamuel Pitoiset2015-08-291-20/+0
* nouveau: avoid build failures since 0fc21ecfIlia Mirkin2015-08-263-3/+3
* gallium: add flags parameter to pipe_screen::context_createMarek Olšák2015-08-266-6/+6
* nv50: fix 2d engine blits for 64- and 128-bit formatsIlia Mirkin2015-08-231-0/+4
* nv50: account for the int RT0 rule for alpha-to-one/covIlia Mirkin2015-08-233-11/+23
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