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* nvc0: check return value of nvc0_program_validate()Samuel Pitoiset2015-12-141-4/+1
| | | | | | | Spotted by Coverity. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* nv50: check return value of nouveau_object_new()Samuel Pitoiset2015-12-141-4/+4
| | | | | | | When ret == 0, obj is not NULL. Spotted by Coverity. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* nv50,nvc0: make use of unreachable() when invalid texture target happensSamuel Pitoiset2015-12-142-5/+2
| | | | | | | Spotted by Coverity. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* gk104/ir: simplify and fool-proof texbar algorithmIlia Mirkin2015-12-122-83/+56
| | | | | | | | | | | | | | With the current algorithm, we only look at tex uses. However there's a write-after-write hazard where we might decide to, on some path, not use a texture's output at all, but instead to write a different value to that register. However without the barrier, the texture might complete later and overwrite that value. This fixes Unreal Elemental demo on GK110/GK208, flightgear on GK10x, and likely other random-looking failures. Signed-off-by: Ilia Mirkin <[email protected]> Cc: "11.1" <[email protected]>
* nv50/ir: combine sequences of conversionsIlia Mirkin2015-12-121-0/+43
| | | | | | | | | | In some cases shaders want non-default rounding when converting float to integer. This can be done in one go, so merge the two ops. This comes up in the packUnorm4x8 & co functions, as well as a few random shaders. Overall shader-db impact is minimal, helping a handful of witcher2 and other misc shaders. Signed-off-by: Ilia Mirkin <[email protected]>
* nv50/ir: manually optimize multiplication expansion logicIlia Mirkin2015-12-121-6/+25
| | | | | | | | | | | | | | | | | | | | | | | | | The conversion of 32-bit integer multiplies into 16-bit ones happens after the regular optimization loop. However it's fairly common to multiply by a small integer, rendering some of the expansion pointless. Firstly, propagate immediates when possible into mul ops, secondly just remove the ops when they are unnecessary. Including the change to generate imad immediates, the effect is: total instructions in shared programs : 6365463 -> 6351898 (-0.21%) total gprs used in shared programs : 728684 -> 728684 (0.00%) total local used in shared programs : 9904 -> 9904 (0.00%) total bytes used in shared programs : 44001576 -> 44036120 (0.08%) local gpr inst bytes helped 0 0 3288 4 hurt 0 0 0 842 It's easy for this to hurt bytes since we end up always generating the 8-byte form, while we can't always get rid of the immediate in question. Signed-off-by: Ilia Mirkin <[email protected]>
* nv50/ir: fix imul emission in the presence of an immediateIlia Mirkin2015-12-121-4/+7
| | | | Signed-off-by: Ilia Mirkin <[email protected]>
* nv50/ir: teach post-ra immediate folding into mad about integersIlia Mirkin2015-12-121-3/+31
| | | | | | | There will usually be a split before the mad op, peer through that and pick out the right word of the immediate. Signed-off-by: Ilia Mirkin <[email protected]>
* nv50/ir: add short imad supportIlia Mirkin2015-12-123-22/+40
| | | | | | | Support emission of the short imad, but also include it in the various logic that tries to make it possible to emit. Signed-off-by: Ilia Mirkin <[email protected]>
* nv50/ir: can't have predication and immediatesIlia Mirkin2015-12-121-0/+3
| | | | | Signed-off-by: Ilia Mirkin <[email protected]> Cc: "11.0 11.1" <[email protected]>
* nv50/ir: fix texture grad for cubemapsIlia Mirkin2015-12-124-7/+6
| | | | | | We were ignoring the partial derivatives on the last dim. Signed-off-by: Ilia Mirkin <[email protected]>
* nv50/ir: fix assumption that prog->maxGPR is in 32-bit reg unitsIlia Mirkin2015-12-122-4/+21
| | | | | | | On NV50, we use 16-bit reg units (to make it all work with half-regs). A few places assumed that it was always in 32-bit units. Signed-off-by: Ilia Mirkin <[email protected]>
* nv50,nvc0: fix use-after-free when vertex buffers are unboundPatrick Rudolph2015-12-092-7/+6
| | | | | | | | | | | | Always reset the vertex bufctx to make sure there's no pointer to an already freed pipe_resource left after unbinding buffers. Fixes use after free crash in nvc0_bufctx_fence(). Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=93004 Signed-off-by: Patrick Rudolph <[email protected]> [imirkin: simplify nvc0 fix, apply to nv50] Signed-off-by: Ilia Mirkin <[email protected]> Cc: "11.0 11.1" <[email protected]>
* nv50/ir: fix cutoff for using r63 vs r127 when replacing zeroIlia Mirkin2015-12-081-1/+2
| | | | | | | | | | | The only effect here is a space savings - 822 programs in shader-db affected with the following overall change: total bytes used in shared programs : 44154976 -> 44139880 (-0.03%) Fixes: 641eda0c (nv50/ir: r63 is only 0 if we are using less than 63 registers) Signed-off-by: Ilia Mirkin <[email protected]> Cc: "11.0 11.1" <[email protected]>
* nv50/ir: prefer to color mad def and src2 with the same colorIlia Mirkin2015-12-081-0/+14
| | | | | | | | | | | | | | | | This allows us to use the short encoding, and potentially fold immediates in later on. total instructions in shared programs : 6379731 -> 6367861 (-0.19%) total gprs used in shared programs : 728502 -> 728683 (0.02%) total local used in shared programs : 9904 -> 9904 (0.00%) total bytes used in shared programs : 44661008 -> 44154976 (-1.13%) local gpr inst bytes helped 0 51 7267 20306 hurt 0 232 125 274 Signed-off-by: Ilia Mirkin <[email protected]>
* nv50/ir: reduce degree limit on ops that can't encode large reg destsIlia Mirkin2015-12-081-3/+34
| | | | | | | Operations that take immediates can only encode registers up to 64. This fixes a shader in a "Powered by Unity" intro. Signed-off-by: Ilia Mirkin <[email protected]>
* nv50/ir: only unspill once ahead of a group of instructionsIlia Mirkin2015-12-081-5/+20
| | | | | | | | | | | | | | | | | | | | | | | We already semi-did this but the list of uses as unsorted, so it was unreliable. Sort the uses by bb and serial, and don't unspill for each instruction in a sequence. (And also don't unspill multiple times for a single instruction that uses the value in question multiple times.) This causes a minor reduction in generated instructions for shader-db (as few programs spill) but more importantly it brings determinism to each run's output. On SM10: total instructions in shared programs : 6387945 -> 6379359 (-0.13%) total gprs used in shared programs : 728544 -> 728544 (0.00%) total local used in shared programs : 9904 -> 9904 (0.00%) local gpr inst bytes helped 0 0 322 322 hurt 0 0 0 0 Signed-off-by: Ilia Mirkin <[email protected]>
* nv50/ir: check if the target supports the new offset before inliningIlia Mirkin2015-12-084-3/+25
| | | | | | Fixes: abd326e81b (nv50/ir: propagate indirect loads into instructions) Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=93300 Signed-off-by: Ilia Mirkin <[email protected]>
* nvc0/ir: fix up mul+add -> mad algebraic opt, enable for integersIlia Mirkin2015-12-073-12/+11
| | | | | | | For some reason this has been disabled for integers ever since codegen was merged, despite there being emission code for IMAD. Seems to work. Signed-off-by: Ilia Mirkin <[email protected]>
* gk110/ir: fix imad sat/hi flag emission for immediate argsIlia Mirkin2015-12-071-8/+3
| | | | | | | | According to nvdisasm both the immediate and non-imm cases use the same bits. Both of these flags are quite rarely set though. Signed-off-by: Ilia Mirkin <[email protected]> Cc: "11.0 11.1" <[email protected]>
* gk104/ir: sampler doesn't matter for txfIlia Mirkin2015-12-071-1/+1
| | | | | | | | | | We actually leave the sampler unset for OP_TXF, which caused the GK104+ logic to treat some texel fetches as indirect. While this works, it's incredibly wasteful. This only happened when the texture was > 0 (since sampler remained == 0). Signed-off-by: Ilia Mirkin <[email protected]> Cc: "11.0 11.1" <[email protected]>
* gk110/ir: fix imul hi emission with limm argIlia Mirkin2015-12-071-2/+2
| | | | | | | The elemental demo hits this case. Signed-off-by: Ilia Mirkin <[email protected]> Cc: "11.0 11.1" <[email protected]>
* gallium/drivers: Sanitize NULL checks into canonical formEdward O'Callaghan2015-12-062-3/+3
| | | | | | | | | | Use NULL tests of the form `if (ptr)' or `if (!ptr)'. They do not depend on the definition of the symbol NULL. Further, they provide the opportunity for the accidental assignment, are clear and succinct. Signed-off-by: Edward O'Callaghan <[email protected]> Signed-off-by: Marek Olšák <[email protected]>
* gallium/drivers: Trivial code-style cleanupEdward O'Callaghan2015-12-062-2/+2
| | | | | Signed-off-by: Edward O'Callaghan <[email protected]> Signed-off-by: Marek Olšák <[email protected]>
* gallium/drivers/nouveau: Make use of ARRAY_SIZE macroEdward O'Callaghan2015-12-0614-22/+20
| | | | | Signed-off-by: Edward O'Callaghan <[email protected]> Signed-off-by: Marek Olšák <[email protected]>
* nv50/ir: fold shl + mul with immediatesIlia Mirkin2015-12-051-0/+16
| | | | | | | | | | | | | | On SM20 this gives: total instructions in shared programs : 6299222 -> 6294240 (-0.08%) total gprs used in shared programs : 944139 -> 944068 (-0.01%) total local used in shared programs : 54116 -> 54116 (0.00%) local gpr inst bytes helped 0 126 2781 2781 hurt 0 55 11 11 Signed-off-by: Ilia Mirkin <[email protected]>
* nv50/ir: propagate indirect loads into instructionsIlia Mirkin2015-12-051-0/+52
| | | | | | | | | | | | | | | | This way $r1 = $r0 + 4; c1[$r1] becomes c1[$r0+4]. On SM35: total instructions in shared programs : 6206257 -> 6185058 (-0.34%) total gprs used in shared programs : 911045 -> 910722 (-0.04%) total local used in shared programs : 39072 -> 39072 (0.00%) local gpr inst bytes helped 0 417 4195 4195 hurt 0 280 0 0 Signed-off-by: Ilia Mirkin <[email protected]>
* nv50/ir: flip shl(add, imm) into add(shl, imm)Ilia Mirkin2015-12-051-4/+34
| | | | | | | | | | | | | | | | | This works when the add also has an immediate. This often happens in address calculations. These addresses can then be inlined as well. On code targeted to SM35: total instructions in shared programs : 6223346 -> 6206257 (-0.27%) total gprs used in shared programs : 911075 -> 911045 (-0.00%) total local used in shared programs : 39072 -> 39072 (0.00%) local gpr inst bytes helped 0 119 3664 3664 hurt 0 74 15 15 Signed-off-by: Ilia Mirkin <[email protected]>
* nvc0: expose a group of performance metrics for SM30 (Kepler)Samuel Pitoiset2015-12-052-2/+8
| | | | | | | This allows to monitor these performance metrics through GL_AMD_performance_monitor. Signed-off-by: Samuel Pitoiset <[email protected]>
* nvc0: re-introduce performance metrics for SM30 (Kepler)Samuel Pitoiset2015-12-052-5/+188
| | | | | | | This implements more performance metrics than the previous support, but some other metrics still need to be figured out. Signed-off-by: Samuel Pitoiset <[email protected]>
* nvc0: remove useless counting operations for MP countersSamuel Pitoiset2015-12-051-101/+5
| | | | | | Those bits were related to old performance metrics support. Signed-off-by: Samuel Pitoiset <[email protected]>
* nvc0: remove old performance metrics support on KeplerSamuel Pitoiset2015-12-052-37/+0
| | | | | | | These performance metrics will be re-introduced in an upcoming patch that will follow the same design as Fermi. Signed-off-by: Samuel Pitoiset <[email protected]>
* nvc0: remove wrong inst_issued HW SM perf counter on KeplerSamuel Pitoiset2015-12-052-3/+0
| | | | | | | inst_issued is performance metric not a hardware event on Kepler (SM30). It will be re-introduced in an upcoming patch. Signed-off-by: Samuel Pitoiset <[email protected]>
* nvc0: add missing HW SM perf counters for SM30 (Kepler)Samuel Pitoiset2015-12-053-0/+10
| | | | | | | SM30 is the compute capability version for GK104/GK106/GK107. This also introduces a new signal group selection called UNK0F. Signed-off-by: Samuel Pitoiset <[email protected]>
* nvc0: fix the comment that describe MP counters storage on KeplerSamuel Pitoiset2015-12-051-0/+5
| | | | Signed-off-by: Samuel Pitoiset <[email protected]>
* nv50/ir: replace zeros in movs as wellIlia Mirkin2015-12-031-2/+1
| | | | | | | | | The original change to put zeroes directly into instructions created conditional mov's with the zero immediate. However that can't be emitted, so make sure to replace the zero with r63. Fixes: 52a800a68 (nv50/ir: allow immediate 0 to be loaded anywhere) Signed-off-by: Ilia Mirkin <[email protected]>
* nv50/ir: fold fma/mad when all 3 args are immediatesIlia Mirkin2015-12-031-0/+30
| | | | | | This happens pretty rarely, but might as well do it when it does. Signed-off-by: Ilia Mirkin <[email protected]>
* nv50/ir: avoid looking at uninitialized srcMods entriesIlia Mirkin2015-12-032-2/+2
| | | | | Signed-off-by: Ilia Mirkin <[email protected]> Cc: "11.0 11.1" <[email protected]>
* nv50/ir: fix DCE to not generate 96-bit loadsIlia Mirkin2015-12-031-1/+31
| | | | | | | | | | A situation where there's a 128-bit load where the last component gets DCE'd causes a 96-bit load to be generated, which no GPU can actually emit. Avoid generating such instructions by scaling back to 64-bit on the first load when splitting. Signed-off-by: Ilia Mirkin <[email protected]> Cc: "11.0 11.1" <[email protected]>
* nv50/ir: fix moves to/from flagsIlia Mirkin2015-12-022-2/+7
| | | | | | | | Noticed this when looking at a trace that caused flags to spill to/from registers. The flags source/destination wasn't encoded correctly according to both envydis and nvdisasm. Signed-off-by: Ilia Mirkin <[email protected]>
* nv50/ir: don't forget to mark flagsDef on cvt in txb loweringIlia Mirkin2015-12-021-1/+1
| | | | | Signed-off-by: Ilia Mirkin <[email protected]> Cc: "11.0 11.1" <[email protected]>
* nv50/ir: fix instruction permutation logicIlia Mirkin2015-12-021-1/+1
| | | | | Signed-off-by: Ilia Mirkin <[email protected]> Cc: "11.0 11.1" <[email protected]>
* nv50/ir: the mad source might not have a defining instructionIlia Mirkin2015-12-021-1/+1
| | | | | | | For example if it's $r63 (aka 0), there won't be a definition. Signed-off-by: Ilia Mirkin <[email protected]> Cc: "11.0 11.1" <[email protected]>
* nv50/ir: make sure entire graph is reachableIlia Mirkin2015-12-021-0/+1
| | | | | | | | The algorithm expects the entire CFG to be reachable, so make sure that we hit every node. Otherwise we will end up with uninitialized data, memory corruption, etc. Signed-off-by: Ilia Mirkin <[email protected]>
* nv50/ir: deal with loops with no breaksIlia Mirkin2015-12-021-0/+6
| | | | | | | | | | | For example if there are only returns, the break bb will not end up part of the CFG. However there will have been a prebreak already emitted for it, and when hitting the RET that comes after, we will try to insert the current (i.e. break) BB into the graph even though it will be unreachable. This makes the SSA code sad. Signed-off-by: Ilia Mirkin <[email protected]> Cc: "11.0 11.1" <[email protected]>
* nvc0/ir: fold postfactor into immediateIlia Mirkin2015-12-021-0/+6
| | | | | | | | SM20-SM50 can't emit a post-factor in the presence of a long immediate. Make sure to fold it in. Signed-off-by: Ilia Mirkin <[email protected]> Cc: "11.0 11.1" <[email protected]>
* nv50/ir: allow immediate 0 to be loaded anywhereIlia Mirkin2015-12-021-0/+6
| | | | | | | There's a post-RA fixup to replace 0's with $r63 (or $r127 if too many regs are used), so just as nvc0, let an immediate 0 be loaded anywhere. Signed-off-by: Ilia Mirkin <[email protected]>
* nv50/ir/gk110: add memory barriers support for GK110Samuel Pitoiset2015-12-021-0/+12
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* nv50/ir: do not call textureMask() for surface opsSamuel Pitoiset2015-12-021-1/+2
| | | | | | | | | | | That texture mask thing doesn't seem to be needed for surface ops, so just as nve4+, let do that only for texture ops. This fixes a segfault with 'test_surface_st' from gallium/tests/trivial/compute.c on Fermi because this test uses sustp. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* nv50,nvc0: allow to create resources other than buffersSamuel Pitoiset2015-12-015-4/+9
| | | | | | | | | | | | For the compute support, we might stick buffers as surfaces. This fixes an assertion when executing src/gallium/tests/trivial/compute. To avoid using these "restricted" surfaces as render targets, these assertions have been moved. Note that it's already handled for the framebuffer thing on nvc0. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
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