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* gallium/nouveau: handle query_renderer capsEmil Velikov2014-08-153-9/+61
| | | | Signed-off-by: Emil Velikov <[email protected]>
* nv50,nvc0: add support for fine derivativesIlia Mirkin2014-08-143-2/+6
| | | | | | | The quadop-based method we currently use on all chipsets already provides the fine version of the derivatives. Signed-off-by: Ilia Mirkin <[email protected]>
* gallium: add opcodes/cap for fine derivative supportIlia Mirkin2014-08-143-0/+3
| | | | | | | Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Marek Olšák <[email protected]> (v1) Reviewed-by: Roland Scheidegger <[email protected]> (v1) v2: Reuse opcode gaps as suggested by Marek
* nvc0: increase GLSL level to 400 to enable ARB_gpu_shader5Ilia Mirkin2014-08-131-1/+1
| | | | Signed-off-by: Ilia Mirkin <[email protected]>
* android: gallium/nouveau: fix include folders, link against libstlportEmil Velikov2014-08-131-4/+5
| | | | | | | | | | | nouveau uses STL for a while now thus we need to include external/stlport/libstlport.mk in order to get the build at least partially working. v2: Use the installed libdrm headers over the DRM_TOP ones. Cc: "10.1 10.2" <[email protected]> Signed-off-by: Emil Velikov <[email protected]>
* nvc0: add BPTC format supportIlia Mirkin2014-08-121-0/+7
| | | | Signed-off-by: Ilia Mirkin <[email protected]>
* nvc0/ir: describe the tex arguments for fermi/keplerIlia Mirkin2014-08-111-0/+25
| | | | Signed-off-by: Ilia Mirkin <[email protected]>
* nvc0/ir: add kepler+ support for indirect texture referencesIlia Mirkin2014-08-111-7/+27
| | | | Signed-off-by: Ilia Mirkin <[email protected]>
* nvc0/ir: add base tex offset for fermi indirect tex caseIlia Mirkin2014-08-111-2/+10
| | | | Signed-off-by: Ilia Mirkin <[email protected]>
* gallium: remove PIPE_SHADER_CAP_MAX_ADDRSMarek Olšák2014-08-113-8/+0
| | | | | | | | | | | | | | | This limit is fixed in Mesa core and cannot be changed. It only affects ARB_vertex_program and ARB_fragment_program. The minimum value for ARB_vertex_program is 1 according to the spec. The maximum value for ARB_vertex_program is limited to 1 by Mesa core. The value should be zero for ARB_fragment_program, because it doesn't support ARL. Finally, drivers shouldn't mess with these values arbitrarily. Reviewed-by: Ilia Mirkin <[email protected]>
* gallium: Move sRGB <-> RGB handling to libmesautilJason Ekstrand2014-08-042-1/+2
| | | | | Signed-off-by: Jason Ekstrand <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* gallium: rename shader cap MAX_CONSTS to MAX_CONST_BUFFER_SIZEMarek Olšák2014-07-283-8/+8
| | | | | | | | | | This new name isn't so confusing. I also changed the gallivm limit, because it looked wrong. Reviewed-by: Brian Paul <[email protected]> v2: use sizeof(float[4])
* nvc0/ir: support 2d constbuf indexingIlia Mirkin2014-07-241-0/+14
| | | | Signed-off-by: Ilia Mirkin <[email protected]>
* gm107/ir: emit LDC subopsIlia Mirkin2014-07-241-0/+1
| | | | Signed-off-by: Ilia Mirkin <[email protected]>
* gk110/ir: emit load constant subopIlia Mirkin2014-07-241-0/+1
| | | | Signed-off-by: Ilia Mirkin <[email protected]>
* nv50/ir: fix phi/union sources when their def has been mergedIlia Mirkin2014-07-241-0/+8
| | | | | | | | | | | | | In a situation where double-register values are used, the phi nodes can still end up being u32 values. They all get merged into one RA node though. When fixing up the merge (which comes after the phi node), the phi node's def would get fixed, but not its sources which would remain at the low register value. This maintains the invariant that a phi node's defs and sources are allocated the same register. Signed-off-by: Ilia Mirkin <[email protected]>
* nv50/ir: fix hard-coded TYPE_U32 sized registerIlia Mirkin2014-07-241-3/+4
| | | | Signed-off-by: Ilia Mirkin <[email protected]>
* nvc0: mark shader header if fp64 is usedIlia Mirkin2014-07-241-0/+2
| | | | Signed-off-by: Ilia Mirkin <[email protected]>
* nv50/ir: keep track of whether the program uses fp64Ilia Mirkin2014-07-242-2/+7
| | | | Signed-off-by: Ilia Mirkin <[email protected]>
* nvc0: make sure that the local memory allocation is aligned to 0x10Ilia Mirkin2014-07-241-1/+1
| | | | | Signed-off-by: Ilia Mirkin <[email protected]> Cc: <[email protected]>
* nv50: fix build failure on m68k due to invalid struct alignment assumptionsThorsten Glaser2014-07-171-0/+5
| | | | | | | | Make alignment assumptions explicit by inserting correct padding with unknown struct members. Reviewed-by: Ilia Mirkin <[email protected]> Cc: <[email protected]>
* nvc0: fix translate path for PRIM_RESTART_WITH_DRAW_ARRAYSChristoph Bumiller2014-07-151-13/+28
| | | | Reviewed-by: Ilia Mirkin <[email protected]>
* nvc0: add support for indirect drawingChristoph Bumiller2014-07-158-30/+220
| | | | Reviewed-by: Ilia Mirkin <[email protected]>
* nouveau: check if a fence has already been signalledIlia Mirkin2014-07-151-0/+3
| | | | | | | nouveau_fence_update does real work unconditionally. Avoid doing that if the fence we're checking on has already been signalled. Signed-off-by: Ilia Mirkin <[email protected]>
* nvc0/ir: add support for interpolating with non-default settingsIlia Mirkin2014-07-093-1/+94
| | | | Signed-off-by: Ilia Mirkin <[email protected]>
* nvc0/ir: fix encoding of offset register into interpolation instructionIlia Mirkin2014-07-091-1/+1
| | | | Signed-off-by: Ilia Mirkin <[email protected]>
* nvc0/ir: account for indirect textures on fermi for txdIlia Mirkin2014-07-091-0/+3
| | | | Signed-off-by: Ilia Mirkin <[email protected]>
* nvc0/ir: unset s/r indirect sources before moving everythingIlia Mirkin2014-07-091-9/+10
| | | | | | | | | With the current logic, it's very likely that s/r indirect sources are right after the "regular" ones. Unset them before moving the texture arguments over rather than after, as one of those arguments would likely have assumed one of the s/r positions. Signed-off-by: Ilia Mirkin <[email protected]>
* gallium: switch dedicated centroid field to interpolation locationIlia Mirkin2014-07-091-1/+1
| | | | | | | | The new location field can be either center, centroid, or sample, which indicates the location that the shader should interpolate at. Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]>
* nvc0: allocate more space before a counter is configuredSamuel Pitoiset2014-07-081-2/+3
| | | | | | | | | On nvc0, a counter can have up to 6 sources instead of only one for nve4+. This fixes a crash when a counter uses more than one source. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* nv50/ir: use unordered_set instead of list to keep track of var usesTobias Klausmann2014-07-084-9/+10
| | | | | | | | | | | The set of variable uses does not need to be ordered in any way, and removing/adding elements is a fairly common operation in various optimization passes. This shortens runtime of piglit test fp-long-alu to ~22s from ~4h Signed-off-by: Tobias Klausmann <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* nvc0/ir: fill offset in properly for TXDIlia Mirkin2014-07-081-13/+43
| | | | | | | | Apparently TXD wants its offset differently than TEX, accepting it in the upper bits of the layer index. Unclear what happens when this is combined with indirect sampler indexing. Signed-off-by: Ilia Mirkin <[email protected]>
* nvc0/ir: use manual TXD when offsets are involvedIlia Mirkin2014-07-081-1/+2
| | | | | | | | | | Something about how we're implementing offsets for TXD is wrong, just flip to the generic quadop-based implementation in that case. This is the minimal fix appropriate for backporting. Signed-off-by: Ilia Mirkin <[email protected]> Cc: <[email protected]>
* nvc0/ir: do quadops on the right texture coordinates for TXDIlia Mirkin2014-07-081-2/+3
| | | | | | | | handleTEX moves the layer as the first argument. This makes sure that the quadops deal with the texture coordinates. Signed-off-by: Ilia Mirkin <[email protected]> Cc: <[email protected]>
* nv50/ir: ignore bias for samplerCubeShadow on nv50Ilia Mirkin2014-07-081-0/+10
| | | | | | | | Unfortunately there's no good way to do this on the nv50 shader isa. Dropping the bias seems preferable to doing the compare post-filtering. Signed-off-by: Ilia Mirkin <[email protected]> Cc: <[email protected]>
* nv50/ir: retrieve shadow compare from first argIlia Mirkin2014-07-081-1/+1
| | | | | | | | This can only happen with texture(samplerCubeShadow, bias), where the compare will be in the first argument. Signed-off-by: Ilia Mirkin <[email protected]> Cc: <[email protected]>
* nvc0: add a memory barrier when there are persistent UBOsIlia Mirkin2014-07-035-4/+57
| | | | | Signed-off-by: Ilia Mirkin <[email protected]> Cc: "10.2" <[email protected]>
* nv50: do an explicit flush on draw when there are persistent buffersIlia Mirkin2014-07-033-2/+50
| | | | | Signed-off-by: Ilia Mirkin <[email protected]> Cc: "10.2" <[email protected]>
* nv50: disable dedicated ubo upload methodIlia Mirkin2014-07-031-0/+7
| | | | | | | | | | The hardware allows multiple simultaneous renders with the same memory-backed constbufs but with each invocation having different values. However in order for that to work, the data has to be streamed in via the right constbuf slot. We weren't doing that for UBOs. Signed-off-by: Ilia Mirkin <[email protected]> Cc: "10.2 10.1" <[email protected]>
* gallium: rename PIPE_CAP_TGSI_VS_LAYER to also have _VIEWPORTIlia Mirkin2014-07-033-3/+3
| | | | | | | | | Now that this cap is used to determine the availability of both, adjust its name to reflect the new reality. Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* nvc0: add missed PIPE_CAP_DRAW_INDIRECTIlia Mirkin2014-07-011-0/+1
| | | | | | | Real support will be forthcoming. For now, avoid the unknown cap error and compiler warning. Signed-off-by: Ilia Mirkin <[email protected]>
* gallium: add facilities for indirect drawingChristoph Bumiller2014-07-022-0/+2
| | | | | | v2: Added comments to util_draw_indirect, clarified and fixed map size. Removed unlikely().
* nvc0: expose 4 vertex streams, use stream ids in xfbIlia Mirkin2014-07-015-2/+5
| | | | Signed-off-by: Ilia Mirkin <[email protected]>
* nvc0/ir: only merge emit/restart for identical streamsIlia Mirkin2014-07-011-3/+10
| | | | Signed-off-by: Ilia Mirkin <[email protected]>
* nvc0/ir: avoid creating restarts with non-0 streamIlia Mirkin2014-07-011-3/+7
| | | | Signed-off-by: Ilia Mirkin <[email protected]>
* nvc0/ir: fix emitting vertex streamIlia Mirkin2014-07-011-7/+8
| | | | Signed-off-by: Ilia Mirkin <[email protected]>
* gallium: add a cap for max vertex streamsIlia Mirkin2014-07-013-0/+5
| | | | | | | Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]>
* gallium: add an index argument to create_queryIlia Mirkin2014-07-015-5/+5
| | | | | | Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]>
* nv50: fix dri3 prime buffer creationAxel Davy2014-06-271-2/+6
| | | | | | | | | This is the same fix than "nvc0: fix dri3 prime buffer creation" Signed-off-by: Axel Davy <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* nvc0: fix dri3 prime buffer creationDave Airlie2014-06-271-1/+1
| | | | | | | | We need to place shared buffers into GART. Reviewed-by: Axel Davy <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
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