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path: root/src/gallium/drivers/nouveau/nv50
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* nv50,nvc0: fix push hint logic in presence of a start offsetIlia Mirkin2017-10-111-2/+1
* gallium: Create a new PIPE_CAP_TILE_RASTER_ORDER for vc4.Eric Anholt2017-10-101-0/+1
* gallium: add PIPE_CAP_TGSI_ANY_REG_AS_ADDRESSMarek Olšák2017-10-061-0/+1
* gallium: add LDEXP TGSI instruction and corresponding capNicolai Hähnle2017-09-291-0/+1
* gallium: Add PIPE_SHADER_CAP_INT64_ATOMICSJan Vesely2017-09-211-0/+1
* gallium: Add PIPE_SHADER_CAP_FP16Jan Vesely2017-09-181-0/+1
* gallium: add PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVENicolai Hähnle2017-09-182-0/+5
* gallium: introduce PIPE_CAP_LOAD_CONSTBUFTimothy Arceri2017-09-151-0/+1
* gallium: introduce PIPE_CAP_MEMOBJTimothy Arceri2017-08-031-0/+1
* gallium: add PIPE_QUERY_SO_OVERFLOW_ANY_PREDICATE and corresponding capNicolai Hähnle2017-08-021-0/+1
* gallium: add PIPE_CAP_NIR_SAMPLERS_AS_DEREFNicolai Hähnle2017-07-311-0/+1
* nv50,nvc0: remove IDX from bufctx immediately, to avoid conflicts with clearIlia Mirkin2017-06-261-4/+5
* gallium: add PIPE_CAP_BINDLESS_TEXTURESamuel Pitoiset2017-06-141-0/+1
* util: Port nir_array functionality to u_dynarrayThomas Helland2017-06-071-1/+1
* gallium: Add a cap to check if the driver supports ARB_post_depth_coverageLyude2017-06-021-0/+1
* nv50,nvc0: clear index buffer bufctx bin unconditionallyIlia Mirkin2017-05-201-3/+2
* nv50: fix vtxbuf cleanupIlia Mirkin2017-05-201-1/+1
* gallium: add PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTIONMarek Olšák2017-05-171-0/+1
* gallium: add PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEXMarek Olšák2017-05-101-0/+1
* gallium: remove pipe_index_buffer and set_index_bufferMarek Olšák2017-05-105-57/+24
* gallium: decrease the size of pipe_vertex_buffer - 24 -> 16 bytesMarek Olšák2017-05-104-19/+20
* nv50/ir: Replace NV50_PROGRAM_IR_* by PIPE_SHADER_IR_*Pierre Moreau2017-05-071-1/+3
* nv50,nvc0: disable the TGSI merge registers passSamuel Pitoiset2017-04-261-1/+2
* gallium: add PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERSSamuel Pitoiset2017-04-261-0/+1
* gallium: add PIPE_CAP_TGSI_TES_LAYER_VIEWPORTNicolai Hähnle2017-04-141-0/+1
* nouveau: enable ARB_shader_clock on nv50 and nvc0Boyan Ding2017-04-091-1/+1
* gallium: add PIPE_CAP_TGSI_BALLOTNicolai Hähnle2017-04-051-0/+1
* gallium: add sparse buffer interface and capabilityNicolai Hähnle2017-04-051-0/+1
* nv50: don't assume a rast is set when validating for clearsIlia Mirkin2017-04-022-3/+7
* gallium: Add a cap to check if the driver supports fill_rectangleLyude2017-03-311-0/+1
* gallium: remove support for predicates from TGSI (v2)Marek Olšák2017-04-011-2/+0
* gallium: add PIPE_CAP_TGSI CLOCKNicolai Hähnle2017-03-311-0/+1
* nv50,nvc0: enable TEX_LZ and TXF_LZIlia Mirkin2017-03-181-1/+1
* gallium: add PIPE_CAP_TGSI_TEX_TXF_LZMarek Olšák2017-03-151-0/+1
* gallium: s/uint/enum pipe_render_cond_flag/ for set_render_condition()Brian Paul2017-03-081-1/+1
* gallium: s/uint/enum pipe_shader_type/ for set_constant_buffer()Brian Paul2017-03-081-1/+2
* gallium: s/unsigned/enum pipe_shader_type/ for pipe_screen::get_shader_param()Brian Paul2017-03-081-1/+2
* gallium/util: replace pipe_mutex_unlock() with mtx_unlock()Timothy Arceri2017-03-071-1/+1
* gallium/util: replace pipe_mutex_lock() with mtx_lock()Timothy Arceri2017-03-071-1/+1
* gallium/util: replace pipe_mutex_destroy() with mtx_destroy()Timothy Arceri2017-03-071-1/+1
* gallium/util: replace pipe_mutex_init() with mtx_init()Timothy Arceri2017-03-071-1/+1
* gallium/util: replace pipe_mutex with mtx_tTimothy Arceri2017-03-071-1/+1
* gallium: remove PIPE_CAP_USER_INDEX_BUFFERSMarek Olšák2017-02-251-1/+0
* gallium: set pipe_context uploaders in drivers (v3)Marek Olšák2017-02-141-0/+11
* nv50,nvc0: use alternate samplers for stencilIlia Mirkin2017-02-121-3/+3
* gallium: add separate PIPE_CAP_INT64_DIVMODIlia Mirkin2017-02-091-0/+1
* gallium: turn PIPE_SHADER_CAP_DOUBLES into a screen capabilityNicolai Hähnle2017-02-021-1/+1
* gallium: Add integer 64 capabilityDave Airlie2017-01-271-0/+1
* nv50: add support for MUL_ZERO_WINS propertyIlia Mirkin2017-01-235-2/+11
* gallium: add PIPE_CAP_TGSI_MUL_ZERO_WINSIlia Mirkin2017-01-231-0/+1
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