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* nvc0/ir: fix overwriting of value backing non-constant gather offsetIlia Mirkin2016-10-101-2/+2
* nv50/ir: only stick one preret per functionIlia Mirkin2016-10-101-4/+7
* nv50/ir: fix wrong check when optimizing MAD to SHLADDSamuel Pitoiset2016-10-071-1/+1
* nv50/ir: set number of threads/block for variable local sizeSamuel Pitoiset2016-10-071-0/+2
* nv50/ir: optimize sub(a, 0) to aKarol Herbst2016-10-061-0/+3
* nv50/ra: let simplify return an error and handle thatKarol Herbst2016-10-051-5/+7
* nv50/ir: teach insnCanLoad() about SHLADDSamuel Pitoiset2016-09-291-0/+2
* nv50/ir: optimize SHLADD(a, b, c) to MOV((a << b) + c)Samuel Pitoiset2016-09-291-0/+3
* nv50/ir: optimize SHLADD(a, b, 0x0) to SHL(a, b)Samuel Pitoiset2016-09-291-0/+8
* nv50/ir: optimize IMAD to SHLADD in presence of power of 2Samuel Pitoiset2016-09-291-0/+7
* nvc0/ir: add emission for SHLADDSamuel Pitoiset2016-09-293-0/+127
* nv50/ir: add preliminary support for SHLADDSamuel Pitoiset2016-09-295-7/+17
* nvc0: update GM107 sched control codes formatSamuel Pitoiset2016-09-291-21/+21
* nv50/ir: fix comments about instructions infoSamuel Pitoiset2016-09-261-2/+3
* nv50/ir: drop unused NVISA_XXX_CHIPSET constantsSamuel Pitoiset2016-09-261-2/+0
* nv50/ir: optimize SUB(a, b) to MOV(a - b)Samuel Pitoiset2016-09-181-0/+10
* gk110/ir: fix wrong emission of OP_NOTSamuel Pitoiset2016-09-181-1/+1
* nvc0/ir: fix subops for IMADSamuel Pitoiset2016-09-171-4/+6
* nvc0/ir: fix comments about instructions infoSamuel Pitoiset2016-09-171-2/+3
* gm107/ir: allow indirect inputs to be loaded by frag shaderIlia Mirkin2016-09-101-4/+21
* gm107/ir: AL2P writes to a predicate registerIlia Mirkin2016-09-101-0/+1
* gk110/ir: fix quadop dall emissionIlia Mirkin2016-09-041-2/+2
* nvc0/ir: allow min/max instructions to be dual-issued in pairsKarol Herbst2016-09-031-2/+12
* nvc0/ir: don't dual-issue ops that depend or interfere with each otherKarol Herbst2016-09-033-14/+23
* nv50/ir: always emit the NDV bit for OP_QUADOPSamuel Pitoiset2016-08-302-8/+2
* nv50/ir: make sure cfg iterator always hits all blocksIlia Mirkin2016-08-231-4/+4
* nv50/ir: fix bb positions after exit instructionsIlia Mirkin2016-08-161-3/+10
* nv50/ir: properly clear upper bits of a bitset fillIlia Mirkin2016-08-161-2/+2
* gm107/ir: add a legalize SSA pass for PFETCHSamuel Pitoiset2016-07-274-2/+43
* nvc0/ir: fix up an assertion in emitUADD()Samuel Pitoiset2016-07-241-4/+3
* nv50/ir: allow to swap sources for OP_SUBSamuel Pitoiset2016-07-221-1/+6
* nv50/ir: print OP_SUREDB subops in debug modeSamuel Pitoiset2016-07-201-0/+1
* gm107/ir: add emission for SUREDxSamuel Pitoiset2016-07-201-0/+50
* gm107/ir: add emission for SUSTx and SULDxSamuel Pitoiset2016-07-201-0/+104
* gm107/ra: fix constraints for surface operationsSamuel Pitoiset2016-07-201-2/+23
* gm107/ir: lower surface operationsSamuel Pitoiset2016-07-202-1/+77
* gm107/ir: make use of ADD32I for all immediatesSamuel Pitoiset2016-07-191-1/+1
* gm107/ir: add missing NEG modifier for IADD32ISamuel Pitoiset2016-07-191-0/+1
* nvc0: add support for BGRA8 imagesIlia Mirkin2016-07-184-0/+11
* nv50: fix alphatest for non-blendable formatsIlia Mirkin2016-07-166-6/+63
* nv50/ir: add missing string for SV_WORK_DIMSamuel Pitoiset2016-07-141-0/+1
* nvc0: initial support for GP100 GPUsBen Skeggs2016-07-122-0/+3
* nvc0/ir: fix images indirect access on FermiSamuel Pitoiset2016-07-111-0/+7
* nvc0/ir: remove unused resource info loading helpersSamuel Pitoiset2016-07-082-28/+0
* nvc0/ir: refactor the surfaces info loading logicSamuel Pitoiset2016-07-082-82/+44
* nvc0/ir: move the shift left op inside loadTexHandle()Samuel Pitoiset2016-07-081-8/+6
* nvc0/ir: rename NVE4_SU_INFO_XXX to NVC0_SU_INFO_XXXSamuel Pitoiset2016-07-051-49/+49
* nvc0/ir: reset the base offset for indirect images accessesSamuel Pitoiset2016-07-051-2/+4
* gm107/ir: fix sign bit emission for FADD32ISamuel Pitoiset2016-07-051-3/+6
* nouveau: Fix a couple of "foo may be used uninitialized' compiler warningsHans de Goede2016-07-021-2/+2
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