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* util: Move util_is_power_of_two to bitscan.h and rename to ↵Ian Romanick2018-03-292-3/+3
| | | | | | | | | | | util_is_power_of_two_or_zero The new name make the zero-input behavior more obvious. The next patch adds a new function with different zero-input behavior. Signed-off-by: Ian Romanick <[email protected]> Suggested-by: Matt Turner <[email protected]> Reviewed-by: Alejandro Piñeiro <[email protected]>
* nvc0/ir: fix emiting NOTs with predicatesKarol Herbst2018-03-291-0/+2
| | | | | Signed-off-by: Karol Herbst <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* nvc0/ir: fix INTERP_* with indirect inputsIlia Mirkin2018-03-271-3/+4
| | | | | | | | | | | | There were two problems, both of which are fixed now: - The indirect address was not being shifted by 4 - The indirect address was being placed as an argument in the offset case This fixes some of the new interpolateAt* piglits which now test for these situations. Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Karol Herbst <[email protected]>
* nvir/gm107: consider FILE_FLAGS dependencies in SchedDataCalculatorGM107Karol Herbst2018-02-261-1/+14
| | | | | | | | | | | | | | | | | | | | currently while insterting barriers, writes and reads to FILE_FLAGS aren't considered. This can lead to WaR hazards in some situations. With the previous commit fixes shaders with intstructions like this: mad u32 $r2 $r4 $r11 $r2 mad u32 { $r5 $c0 } $r4 $r10 $r6 mad (SUBOP:1) u32 $r3 $r4 $r10 $r2 $c0 Affects OpenCL CTS tests on Maxwell+: basic/test_basic intmath_long basic/test_basic intmath_long2 basic/test_basic intmath_long4 v2: only put barriers on instructions which actually read flags Reviewed-by: Samuel Pitoiset <[email protected]> Signed-off-by: Karol Herbst <[email protected]>
* nvir/gm107: iterate over all defs in SchedDataCalculatorGM107::findFirstUseKarol Herbst2018-02-261-16/+18
| | | | | | | | | | In the sched data calculator we have to track first use of defs by iterating over all defs of an instruction, not just the first one. v2: fix minGRP and maxGRP values Reviewed-by: Samuel Pitoiset <[email protected]> Signed-off-by: Karol Herbst <[email protected]>
* nvir: dont optimize mad with subops to shladdKarol Herbst2018-02-241-1/+2
| | | | | Signed-off-by: Karol Herbst <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* nvir/nvc0: fix legalizing of ld unlock c0[0x10000]Karol Herbst2018-02-211-1/+1
| | | | | | | | | We have to increase the file index also for 0x10000 not just for values greater than 0x10000. Fixes: 37b67db6ae34fb6586d640a7a1b6232f091dd812 Signed-off-by: Karol Herbst <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* gm107/ir: avoid using kepler instruction capabilitiesIlia Mirkin2018-02-172-21/+45
| | | | | | | | Split up the op properties table into generation-specific bits, and only use the kepler ones on kepler. Fixes some CTS images tests. Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Karol Herbst <[email protected]>
* nvc0: add support for bindless on maxwell+Ilia Mirkin2018-02-171-9/+23
| | | | Signed-off-by: Ilia Mirkin <[email protected]>
* gm107/ir: change how SUQ works in preparation for bindlessIlia Mirkin2018-02-173-1/+61
| | | | | | | All this information can be retrieved from the TIC directly. Avoid having to dip into the constbuf information about the image. Signed-off-by: Ilia Mirkin <[email protected]>
* nvc0: add bindless image support for keplerIlia Mirkin2018-01-074-57/+151
| | | | | | | | A part of the driver constbuf area is allocated for bindless images. Any update requires uploading to all driver constbufs. This also extends the driver constbuf to 64KB, up from 2KB. Signed-off-by: Ilia Mirkin <[email protected]>
* nvc0: add support for bindless textures on kepler+Ilia Mirkin2018-01-073-4/+17
| | | | | | | | | This keeps a list of resident textures (per context), and dumps that list into the active buffer list when submitting. We also treat bindless texture fetches slightly differently, wrt the meaning of indirect, and not requiring the SAMPLER file to be used. Signed-off-by: Ilia Mirkin <[email protected]>
* nv50/ir: use the image info in the instruction rather than declIlia Mirkin2018-01-071-52/+24
| | | | | | | | | | In preparation for bindless images, we have to retrieve the target/format info from the instruction directly, as there will be no declaration. Furthermore, for bound images, this information is still available in the instruction, so we can drop the declaration-based mechanism entirely. Signed-off-by: Ilia Mirkin <[email protected]>
* nvc0/ir: safen up lowering logic against overwriting reused valuesIlia Mirkin2018-01-071-2/+4
| | | | | | | | | I'm fairly sure both of the changed sites are OK as-is, but they're fragile, so this is just safening them up. Since this is happening pre-ssa, we don't want to be overwriting values that may potentially get used later on. Signed-off-by: Ilia Mirkin <[email protected]>
* nv50/ir: Fix unused var warnings in release buildRhys Kidd2017-12-292-2/+4
| | | | | | | | v2: Add preventative comment (Ilia Mirkin) Reviewed-by: Eric Engestrom <[email protected]> Reviewed-by: Pierre Moreau <[email protected]> Signed-off-by: Rhys Kidd <[email protected]>
* gm107/ir: use lane 0 for manual textureGrad handlingIlia Mirkin2017-12-221-21/+34
| | | | | | | | | | This is parallel to the pre-SM50 change which does this. Adjusts the shuffles / quadops to make the values correct relative to lane 0, and then splat the results to all lanes for the final move into the target register. Signed-off-by: Ilia Mirkin <[email protected]> Tested-By: Karol Herbst <[email protected]>
* nvc0/ir: change textureGrad to always use lane 0 as the tex originIlia Mirkin2017-12-191-14/+46
| | | | | | | | | | | | | | | | | | | Thanks to Karol Herbst for the debugging / tracing work that led to this change. Move to using lane 0 as the "work" lane for the texture. It is unclear why this helps, as that computation should be identical to doing it in the "correct" lane with the properly adjusted quadops. In order to be able to use the lane 0 result, we also have to ensure that lane 0 contains the proper array/indirect/shadow values. This applies to Fermi and Kepler. Maxwell+ may or may not need fixing, but that lowering logic is separate. Fixes KHR-GL45.texture_cube_map_array.sampling Signed-off-by: Ilia Mirkin <[email protected]>
* nvc0/ir: Properly lower 64-bit shifts when the shift value is >32Pierre Moreau2017-12-041-1/+1
| | | | | | | | | | | | | | | | | | | | Fixes: 61d7676df77 "nvc0/ir: add support for 64-bit shift lowering on SM20/SM30" Fixes fs-shift-scalar-by-scalar.shader_test from piglit for the current set-up: uniform int64_t ival -0x7dfcfefbdf6536ff # bit pattern: 0x82030104209ac901 uniform uint64_t uval 0x1400000085010203 uniform int shl 36 uniform int shr 36 uniform int64_t iexpected_shl 0x09ac901000000000 uniform int64_t iexpected_shr -0x7dfcff0 # bit pattern: 0xfffffffff8203010 uniform uint64_t uexpected_shl 0x5010203000000000 uniform uint64_t uexpected_shr 0x0000000001400000 draw rect ortho 12 0 4 4 Signed-off-by: Pierre Moreau <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* nouveau/compiler: Allow to omit line numbers when printing instructionsTobias Klausmann2017-11-262-4/+10
| | | | | | | | | | | | | | | | This comes in handy when checking "NV50_PROG_DEBUG=1" outputs with diff! V2: - Use environmental variable (Karol Herbst) V3: - Use the already populated nv50_ir_prog_info to forward information to the print pass (Pierre Moreau) V4: - get rid of default value in PrintPass constructor Signed-off-by: Tobias Klausmann <[email protected]> Reviewed-by: Pierre Moreau <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* nv50/ir: move LateAlgebraicOpt to the very endIlia Mirkin2017-11-261-1/+1
| | | | | | | | | | | | | | | | | | | | | | Memory loads can take offsets, but the SHLADD will often attempt to consume the offsets too. As there may be multiple memory loads with the same base but different offsets, those would end up in a SHLADD instead of the offset of the memory operation. This moves the pass after we've had a chance to attempt to propagate immediate adds into the indirect offset. total instructions in shared programs : 6580681 -> 6567716 (-0.20%) total gprs used in shared programs : 944261 -> 943375 (-0.09%) total shared used in shared programs : 0 -> 0 (0.00%) total local used in shared programs : 15328 -> 15328 (0.00%) total bytes used in shared programs : 60339896 -> 60221504 (-0.20%) local shared gpr inst bytes helped 0 0 555 2698 2698 hurt 0 0 138 336 336 Signed-off-by: Ilia Mirkin <[email protected]>
* nv50/ir: when merging immediates/consts, load directlyIlia Mirkin2017-11-261-1/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | When a MERGE operation gets its constraint moves added, it susbstantially extends live ranges to be reusing an immediate from earlier in the program (not to mention the silliness of loading an immediate into a register, and then moving into another register). We detect these scenarios and insert moves that take the immediate or constbuf load directly into the register. If it's the last use, then we can just move that operation to the closer location. With SM35 (255 regs) we get these results: total instructions in shared programs : 6583670 -> 6580681 (-0.05%) total gprs used in shared programs : 950818 -> 944261 (-0.69%) total shared used in shared programs : 0 -> 0 (0.00%) total local used in shared programs : 15328 -> 15328 (0.00%) total bytes used in shared programs : 60367456 -> 60339896 (-0.05%) local shared gpr inst bytes helped 0 0 4584 3186 3186 hurt 0 0 55 968 968 I suspect they will be better for SM20 and SM30. Signed-off-by: Ilia Mirkin <[email protected]>
* nv50/ir: add optimization for modulo by a non-power-of-2 valueIlia Mirkin2017-11-261-0/+15
| | | | | | | | We can still use the optimized division methods which make use of multiplication with overflow. Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Tobias Klausmann <[email protected]>
* nv50/ir: optimize signed integer modulo by pow-of-2Ilia Mirkin2017-11-252-10/+29
| | | | | | | | | It's common to use signed int modulo in GLSL. As it happens, the GLSL specs allow the result to be undefined, but that seems fairly surprising. It's not that much more effort to get it right, at least for positive modulo operators. Signed-off-by: Ilia Mirkin <[email protected]>
* nv50/ir: Store shared memory per block in nv50_ir_prog_infoPierre Moreau2017-11-041-0/+1
| | | | Signed-off-by: Pierre Moreau <[email protected]>
* nv50/ir: fix 64-bit integer shiftsIlia Mirkin2017-10-091-1/+3
| | | | | | | | | TGSI was adjusted to always pass in 64-bit integers but nouveau was left with the old semantics. Update to the new thing. Fixes: d10fbe5159 (st/glsl_to_tgsi: fix 64-bit integer bit shifts) Reported-by: Karol Herbst <[email protected]> Cc: [email protected]
* nvc0/ir: propagate immediates to CALL input MOVsTobias Klausmann2017-08-311-2/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On using builtin functions we have to move the input to registers $0 and $1, if one of the input value is an immediate, we fail to propagate the immediate: ... mov u32 $r477 0x00000003 (0) ... mov u32 $r0 %r473 (0) mov u32 $r1 $r477 (0) call abs BUILTIN:0 (0) mov u32 %r495 $r1 (0) ... With this patch the immediate is propagated, potentially causing the first MOV to be superfluous, which we'd remove in that case: ... mov u32 $r0 %r473 (0) mov u32 $r1 0x00000003 (0) call abs BUILTIN:0 (0) mov u32 %r495 $r1 (0) ... Shaderdb stats: total instructions in shared programs : 4893460 -> 4893324 (-0.00%) total gprs used in shared programs : 582972 -> 582881 (-0.02%) total local used in shared programs : 17960 -> 17960 (0.00%) local gpr inst bytes helped 0 91 112 112 hurt 0 0 0 0 v2: implement some changes proposed by imirkin, the manual deletion of the dead mov is necessary after ea22ac23e0 ("nvc0/ir: unlink values pre- and post-call to division function") as the potentially dead mov is unlinked properly, causing later passes to not notice the mov op at all and thus not cleaning it up. That makes up a big chunk of the regression the above commit caused. Keep the deletion of the op where it is, deleting it later unnecessarily blows up size of the change. Signed-off-by: Tobias Klausmann <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* nv50/ir: properly set sType for TXF ops to U32Ilia Mirkin2017-08-241-0/+3
| | | | | | | | | | | | All of the coordinates and LOD args are integers for TXF. This mostly doesn't matter, except for converting into a levelZero=true operation by removing an explicit zero LOD. For the comparison against zero to work properly, the sType of the instruction has to be set correctly. Fixes: KHR-GL45.robust_buffer_access_behavior.texel_fetch Reported-by: Karol Herbst <[email protected]> Signed-off-by: Ilia Mirkin <[email protected]> Cc: [email protected]
* gallium: remove TGSI opcode SCSMarek Olšák2017-08-221-14/+0
| | | | | | | use COS+SIN instead. Reviewed-by: Roland Scheidegger <[email protected]> Acked-by: Jose Fonseca <[email protected]>
* gallium: remove TGSI opcode XPDMarek Olšák2017-08-221-27/+0
| | | | | | use MUL+MAD+MOV instead. Reviewed-by: Roland Scheidegger <[email protected]>
* gallium: remove TGSI opcode DPHMarek Olšák2017-08-221-8/+0
| | | | | | use DP4 or DP3 + ADD. Reviewed-by: Roland Scheidegger <[email protected]>
* gallium: remove TGSI FENCE opcodesMarek Olšák2017-08-221-10/+0
| | | | | | use MEMBAR instead Reviewed-by: Roland Scheidegger <[email protected]>
* gallium: remove TGSI opcodes PUSHA, POPA, SAD, TXQ_LZMarek Olšák2017-08-221-3/+0
| | | | Reviewed-by: Roland Scheidegger <[email protected]>
* nv50/ir: fix TXQ srcMaskIlia Mirkin2017-08-161-0/+2
| | | | | | | | src0.x is always read for the LOD, irrespective of which outputs are read. Signed-off-by: Ilia Mirkin <[email protected]> Cc: [email protected]
* nv50/ir: fix srcMask computation for TG4 and TXFIlia Mirkin2017-08-161-0/+2
| | | | | | | | | | | This affects which inputs are marked as used. In a situation where only the texture instruction uses an input, it might have been ignored as unused due to input masks. Affects subtests of KHR-GL45.texture_cube_map_array.sampling Signed-off-by: Ilia Mirkin <[email protected]> Cc: [email protected]
* nv50/ir: clean up saturated values immediatelyIlia Mirkin2017-08-121-1/+6
| | | | | | | | | | | | Since we don't iterate to a fixed point, we can end up in situations where we have a SAT instruction + a long immediate. This is not legal. However since it's immediately computable, just run unary straight away to handle the situation. Fixes: 24a799ad35a82 ("nv50/ir: fix ConstantFolding with saturation") Reported-by: Tobias Klausmann <[email protected]> Signed-off-by: Ilia Mirkin <[email protected]> Cc: [email protected]
* nvc0/ir: unlink values pre- and post-call to division functionIlia Mirkin2017-08-121-4/+3
| | | | | | | | | While technically correct, this can lead to e.g. getImmediate assuming that it can walk up the value chain. It could be fixed to not do this, but it seems easier and less error-prone to just not link the two values to save on one LValue object. Signed-off-by: Ilia Mirkin <[email protected]>
* nv50/ir: fix ConstantFolding with saturationKarol Herbst2017-08-092-0/+9
| | | | | | | | | | | | | | | | | For mul(a, +-1) codegen can generate OP_MOV with a saturation flag set which is ignored at emission. The same can happen with add(a, 0), and others. Adding an assert for detecting more of such issues. Fixes wrongly rendered water in Hitman Absolution running under wine. Also a few shaders in Mad Max and Alien Isolation produce such MOVs. CC: <[email protected]> Signed-off-by: Karol Herbst <[email protected]> Reviewed-by: Tobias Klausmann <[email protected]> [imirkin: generalize the fix for other cases] Reviewed-by: Ilia Mirkin <[email protected]>
* nv50/ir: disable mul+add to mad for precise instructionsKarol Herbst2017-07-211-2/+3
| | | | | | | | | | | | fixes missrendering in TombRaider KHR-GL44.gpu_shader5.precise_qualifier KHR-GL45.gpu_shader5.precise_qualifier v4: disable opt only for MAD, it's fine for SAD Signed-off-by: Karol Herbst <[email protected]> Reviewed-by: Pierre Moreau <[email protected]>
* nv50/ir/tgsi: handle precise for most ALU instructionsKarol Herbst2017-07-211-0/+2
| | | | | Signed-off-by: Karol Herbst <[email protected]> Reviewed-by: Pierre Moreau <[email protected]>
* nv50/ir: add precise field to InstructionKarol Herbst2017-07-212-0/+3
| | | | | | | v4: initialize field with NULL Signed-off-by: Karol Herbst <[email protected]> Reviewed-by: Pierre Moreau <[email protected]>
* nv50/ir: fix threads calculation for non-compute shadersIlia Mirkin2017-07-121-5/+9
| | | | | | | | | | We were using the "cp" union fields, which are only valid for compute shaders. The threads calculation affects the available GPRs, so just pick a small number for other shader types to avoid limiting available registers. Signed-off-by: Ilia Mirkin <[email protected]> Cc: [email protected]
* nv50/ir: fix combineLd/St to update existing records as necessaryIlia Mirkin2017-06-261-0/+8
| | | | | | | | | | | | | | | | | | | | | Previously the logic would decide that the record is kept, which translates into keep = false in the caller, which meant that these passes did not run. While it's right that keep = false which means that a new record does not need to be added, we do still have to perform the usual list maintenance. It's easiest to do this pre-merge rather than post. The lowering that clip/cull distance passes produce triggers this bug in TCS (since reading outputs is done differently in other stages), but it should be possible to achieve it with the right sequence of regular reads/writes. Fixes: KHR-GL45.cull_distance.functional Fixes: generated_tests/spec/arb_tessellation_shader/execution/tes-input/tes-input-gl_ClipDistance.shader_test Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]> Cc: [email protected]
* nv50/ir: adjust overlapping logic to take fileIndex-relative offsetsIlia Mirkin2017-06-261-1/+5
| | | | | | | | | | | | | | | If the fileIndex is different, that means they are in logically different spaces. However if there's also a relative offset, then they could end up pointing at the same spot again. Also add a note about potential for multiple buffers to overlap even if they're at different file indexes. However that's potentially lowered away by the point that this logic hits. Not known to fix any specific application or test. Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]>
* nv50/ir: VFETCH is also considered a load for MemoryOptIlia Mirkin2017-06-261-1/+1
| | | | | | | | This has no effect since in practice this will only play for memory-backed files, for which VFETCH will never happen. Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]>
* nv50/ir: fetch indirect sources BEFORE the op that uses themIlia Mirkin2017-06-261-19/+32
| | | | | | | | | | All the BuildUtil helpers just insert the operation into the current BB. So we have to take care that any fetchSrc() operations happen before the operation whose setIndirect() it goes into. Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]> Cc: [email protected]
* nv50/ir: Properly fold constants in SPLIT operationPierre Moreau2017-06-251-3/+4
| | | | | | | Fixes: b7d9677d ("nv50/ir: constant fold OP_SPLIT") Cc: [email protected] Signed-off-by: Pierre Moreau <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* nvc0: Add support for ARB_post_depth_coverageLyude2017-06-022-0/+4
| | | | | Reviewed-by: Samuel Pitoiset <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* nouveau: drop Android 4.4 and earlier supportRob Herring2017-05-252-33/+3
| | | | | | | | | Support for Android 4.4 and earlier has already been removed from mesa. Remove this remaining piece from nouveau, too. Reviewed-by: Ilia Mirkin <[email protected]> Reviewed-by: Emil Velikov <[email protected]> Signed-off-by: Rob Herring <[email protected]>
* nvc0/ir: SHLADD's middle source must be an immediateIlia Mirkin2017-05-201-0/+2
| | | | | | | | The instruction encodings only allow for immediates. Don't try to replace a zero (which is dumb to have in that op in any case) with RZ. Signed-off-by: Ilia Mirkin <[email protected]> Cc: [email protected]
* nv50/ir: Report wrong prog types using proper varPierre Moreau2017-05-131-1/+1
| | | | | | | | | | | | Coverity caught the use of the uninitialised variable `type`. However, it was `info->type`, which is initialised, which was meant to be used. CID: 1406000 Reported-by: Ilia Mirkin <[email protected]> Fixes: b490ca9a387d ("nv50/ir: Fail if encountering unknown shader type") Signed-off-by: Pierre Moreau <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]>
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