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* util: Move util_is_power_of_two to bitscan.h and rename to util_is_power_of_t...Ian Romanick2018-03-292-3/+3
* nvc0/ir: fix emiting NOTs with predicatesKarol Herbst2018-03-291-0/+2
* nvc0/ir: fix INTERP_* with indirect inputsIlia Mirkin2018-03-271-3/+4
* nvir/gm107: consider FILE_FLAGS dependencies in SchedDataCalculatorGM107Karol Herbst2018-02-261-1/+14
* nvir/gm107: iterate over all defs in SchedDataCalculatorGM107::findFirstUseKarol Herbst2018-02-261-16/+18
* nvir: dont optimize mad with subops to shladdKarol Herbst2018-02-241-1/+2
* nvir/nvc0: fix legalizing of ld unlock c0[0x10000]Karol Herbst2018-02-211-1/+1
* gm107/ir: avoid using kepler instruction capabilitiesIlia Mirkin2018-02-172-21/+45
* nvc0: add support for bindless on maxwell+Ilia Mirkin2018-02-171-9/+23
* gm107/ir: change how SUQ works in preparation for bindlessIlia Mirkin2018-02-173-1/+61
* nvc0: add bindless image support for keplerIlia Mirkin2018-01-074-57/+151
* nvc0: add support for bindless textures on kepler+Ilia Mirkin2018-01-073-4/+17
* nv50/ir: use the image info in the instruction rather than declIlia Mirkin2018-01-071-52/+24
* nvc0/ir: safen up lowering logic against overwriting reused valuesIlia Mirkin2018-01-071-2/+4
* nv50/ir: Fix unused var warnings in release buildRhys Kidd2017-12-292-2/+4
* gm107/ir: use lane 0 for manual textureGrad handlingIlia Mirkin2017-12-221-21/+34
* nvc0/ir: change textureGrad to always use lane 0 as the tex originIlia Mirkin2017-12-191-14/+46
* nvc0/ir: Properly lower 64-bit shifts when the shift value is >32Pierre Moreau2017-12-041-1/+1
* nouveau/compiler: Allow to omit line numbers when printing instructionsTobias Klausmann2017-11-262-4/+10
* nv50/ir: move LateAlgebraicOpt to the very endIlia Mirkin2017-11-261-1/+1
* nv50/ir: when merging immediates/consts, load directlyIlia Mirkin2017-11-261-1/+21
* nv50/ir: add optimization for modulo by a non-power-of-2 valueIlia Mirkin2017-11-261-0/+15
* nv50/ir: optimize signed integer modulo by pow-of-2Ilia Mirkin2017-11-252-10/+29
* nv50/ir: Store shared memory per block in nv50_ir_prog_infoPierre Moreau2017-11-041-0/+1
* nv50/ir: fix 64-bit integer shiftsIlia Mirkin2017-10-091-1/+3
* nvc0/ir: propagate immediates to CALL input MOVsTobias Klausmann2017-08-311-2/+19
* nv50/ir: properly set sType for TXF ops to U32Ilia Mirkin2017-08-241-0/+3
* gallium: remove TGSI opcode SCSMarek Olšák2017-08-221-14/+0
* gallium: remove TGSI opcode XPDMarek Olšák2017-08-221-27/+0
* gallium: remove TGSI opcode DPHMarek Olšák2017-08-221-8/+0
* gallium: remove TGSI FENCE opcodesMarek Olšák2017-08-221-10/+0
* gallium: remove TGSI opcodes PUSHA, POPA, SAD, TXQ_LZMarek Olšák2017-08-221-3/+0
* nv50/ir: fix TXQ srcMaskIlia Mirkin2017-08-161-0/+2
* nv50/ir: fix srcMask computation for TG4 and TXFIlia Mirkin2017-08-161-0/+2
* nv50/ir: clean up saturated values immediatelyIlia Mirkin2017-08-121-1/+6
* nvc0/ir: unlink values pre- and post-call to division functionIlia Mirkin2017-08-121-4/+3
* nv50/ir: fix ConstantFolding with saturationKarol Herbst2017-08-092-0/+9
* nv50/ir: disable mul+add to mad for precise instructionsKarol Herbst2017-07-211-2/+3
* nv50/ir/tgsi: handle precise for most ALU instructionsKarol Herbst2017-07-211-0/+2
* nv50/ir: add precise field to InstructionKarol Herbst2017-07-212-0/+3
* nv50/ir: fix threads calculation for non-compute shadersIlia Mirkin2017-07-121-5/+9
* nv50/ir: fix combineLd/St to update existing records as necessaryIlia Mirkin2017-06-261-0/+8
* nv50/ir: adjust overlapping logic to take fileIndex-relative offsetsIlia Mirkin2017-06-261-1/+5
* nv50/ir: VFETCH is also considered a load for MemoryOptIlia Mirkin2017-06-261-1/+1
* nv50/ir: fetch indirect sources BEFORE the op that uses themIlia Mirkin2017-06-261-19/+32
* nv50/ir: Properly fold constants in SPLIT operationPierre Moreau2017-06-251-3/+4
* nvc0: Add support for ARB_post_depth_coverageLyude2017-06-022-0/+4
* nouveau: drop Android 4.4 and earlier supportRob Herring2017-05-252-33/+3
* nvc0/ir: SHLADD's middle source must be an immediateIlia Mirkin2017-05-201-0/+2
* nv50/ir: Report wrong prog types using proper varPierre Moreau2017-05-131-1/+1
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