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* nv50/ir: fold shl + mul with immediatesIlia Mirkin2015-12-051-0/+16
* nv50/ir: propagate indirect loads into instructionsIlia Mirkin2015-12-051-0/+52
* nv50/ir: flip shl(add, imm) into add(shl, imm)Ilia Mirkin2015-12-051-4/+34
* nv50/ir: replace zeros in movs as wellIlia Mirkin2015-12-031-2/+1
* nv50/ir: fold fma/mad when all 3 args are immediatesIlia Mirkin2015-12-031-0/+30
* nv50/ir: avoid looking at uninitialized srcMods entriesIlia Mirkin2015-12-032-2/+2
* nv50/ir: fix DCE to not generate 96-bit loadsIlia Mirkin2015-12-031-1/+31
* nv50/ir: fix moves to/from flagsIlia Mirkin2015-12-022-2/+7
* nv50/ir: don't forget to mark flagsDef on cvt in txb loweringIlia Mirkin2015-12-021-1/+1
* nv50/ir: fix instruction permutation logicIlia Mirkin2015-12-021-1/+1
* nv50/ir: the mad source might not have a defining instructionIlia Mirkin2015-12-021-1/+1
* nv50/ir: make sure entire graph is reachableIlia Mirkin2015-12-021-0/+1
* nv50/ir: deal with loops with no breaksIlia Mirkin2015-12-021-0/+6
* nvc0/ir: fold postfactor into immediateIlia Mirkin2015-12-021-0/+6
* nv50/ir: allow immediate 0 to be loaded anywhereIlia Mirkin2015-12-021-0/+6
* nv50/ir/gk110: add memory barriers support for GK110Samuel Pitoiset2015-12-021-0/+12
* nv50/ir: do not call textureMask() for surface opsSamuel Pitoiset2015-12-021-1/+2
* nv50/ir: always display the opcode number for unknown instructionsSamuel Pitoiset2015-11-292-2/+2
* nv50/ir: fix (un)spilling of 3-wide resultsIlia Mirkin2015-11-221-4/+42
* nvc0/ir: actually emit AFETCH on keplerIlia Mirkin2015-11-181-0/+3
* nvc0/ir: add support for TGSI_SEMANTIC_HELPER_INVOCATIONIlia Mirkin2015-11-126-0/+6
* nv50/ir: fix emission of s[] args in certain situationsIlia Mirkin2015-11-071-2/+2
* nv50/ir: only take abs value when computing high resultIlia Mirkin2015-11-071-1/+1
* nv50/ir: allow emission of immediates in imul/imad opsIlia Mirkin2015-11-071-2/+8
* nv50/ir: properly set the type of the constant folding resultIlia Mirkin2015-11-061-4/+4
* nv50/ir: add support for const-folding OP_CVT with F64 source/destIlia Mirkin2015-11-063-0/+45
* nv50/ir: add fp64 opcode emission support for G200 (NVA0)Ilia Mirkin2015-11-061-10/+84
* nv50/ir: Add support for 64bit immediates to checkSwapSrc01Hans de Goede2015-11-061-5/+6
* nvc0/ir: Teach insnCanLoad about double immediatesHans de Goede2015-11-061-6/+19
* nv50/ir: Add support for merge-s to the ConstantFolding passHans de Goede2015-11-061-0/+15
* nv50/ir: disallow 64-bit immediates on nv50 targetsIlia Mirkin2015-11-061-1/+1
* nv50/ir: allow movs with TYPE_F64 destinations to be splitIlia Mirkin2015-11-061-0/+6
* gm107/ir: Add support for double immediatesHans de Goede2015-11-061-1/+4
* nvc0/ir: Add support for double immediatesHans de Goede2015-11-061-0/+8
* nv50,nvc0: provide debug messages with shader compilation statsIlia Mirkin2015-11-052-0/+3
* nouveau: get rid of tabsIlia Mirkin2015-10-313-4/+4
* nv50: allow per-sample interpolation to be forced via rastIlia Mirkin2015-10-293-3/+29
* nv50/ir: adapt to new method for passing in cull/clip distance masksIlia Mirkin2015-10-293-8/+10
* nvc0: do upload-time fixups for interpolation parametersIlia Mirkin2015-10-297-9/+157
* nv50/ir: use C++11 standard std::unordered_map if possibleChih-Wei Huang2015-10-151-3/+17
* nvc0/ir: start offset at texBindBase for txq, like regular texturingIlia Mirkin2015-09-141-1/+4
* nv50/ir: add support for TXQS tgsi opcodeIlia Mirkin2015-09-133-7/+39
* nv50/ir: don't fold immediate into mad if registers are too highIlia Mirkin2015-09-101-0/+4
* nv50/ir: fix emission of 8-byte wide interp instructionIlia Mirkin2015-09-101-5/+6
* nv50/ir: r63 is only 0 if we are using less than 63 registersIlia Mirkin2015-09-101-1/+4
* nv50/ir: make edge splitting fix up phi node sourcesIlia Mirkin2015-09-101-13/+77
* nouveau: android: add space before PRIx64 macroMauro Rossi2015-09-091-1/+1
* nv50/ir: pre-compute BFE arg when both bits and offset are immIlia Mirkin2015-08-201-3/+9
* nv50/ir: Handle OP_CVT when folding constant expressionsTobias Klausmann2015-08-201-0/+78
* nvc0/ir: undo more shifts still by allowing a pre-SHL to occurIlia Mirkin2015-08-201-15/+33
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