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path: root/src/gallium/drivers/nouveau/codegen
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* nv50/ir: use C++11 standard std::unordered_map if possibleChih-Wei Huang2015-10-151-3/+17
* nvc0/ir: start offset at texBindBase for txq, like regular texturingIlia Mirkin2015-09-141-1/+4
* nv50/ir: add support for TXQS tgsi opcodeIlia Mirkin2015-09-133-7/+39
* nv50/ir: don't fold immediate into mad if registers are too highIlia Mirkin2015-09-101-0/+4
* nv50/ir: fix emission of 8-byte wide interp instructionIlia Mirkin2015-09-101-5/+6
* nv50/ir: r63 is only 0 if we are using less than 63 registersIlia Mirkin2015-09-101-1/+4
* nv50/ir: make edge splitting fix up phi node sourcesIlia Mirkin2015-09-101-13/+77
* nouveau: android: add space before PRIx64 macroMauro Rossi2015-09-091-1/+1
* nv50/ir: pre-compute BFE arg when both bits and offset are immIlia Mirkin2015-08-201-3/+9
* nv50/ir: Handle OP_CVT when folding constant expressionsTobias Klausmann2015-08-201-0/+78
* nvc0/ir: undo more shifts still by allowing a pre-SHL to occurIlia Mirkin2015-08-201-15/+33
* nvc0/ir: don't require AND when the high byte is being addressedIlia Mirkin2015-08-201-0/+12
* nvc0/ir: detect i2f/i2i which operate on specific bytes/wordsIlia Mirkin2015-08-204-4/+82
* nvc0/ir: detect AND/SHR pairs and convert into EXTBFIlia Mirkin2015-08-201-20/+46
* nv50/ir: support different unordered_set implementationsChih-Wei Huang2015-08-205-12/+57
* gk110/ir: fix sched calculator to consider all registers in the ISAIlia Mirkin2015-08-171-7/+10
* gm107/ir: avoid letting the lowering pass get out of syncIlia Mirkin2015-08-172-88/+5
* gm107/ir: indirect handle goes first on maxwell alsoIlia Mirkin2015-08-141-8/+4
* nvc0/ir: cache vertex out base so that we don't recompute againIlia Mirkin2015-07-291-8/+15
* nvc0/ir: output base for reading is based on laneidIlia Mirkin2015-07-291-0/+25
* nvc0/ir: trim out barrier sync for non-compute shadersIlia Mirkin2015-07-281-0/+6
* nvc0/ir: fix barrier emissionIlia Mirkin2015-07-281-0/+2
* nvc0/ir: per-patch vars are in a separate address spaceIlia Mirkin2015-07-241-0/+2
* nvc0/ir: kepler can't do indirect shader input/output loads directlyIlia Mirkin2015-07-238-6/+75
* nvc0/ir: tess factors are now sysvals, adapt codegen to expect thatIlia Mirkin2015-07-236-11/+24
* gk110/ir: fake BAR supportIlia Mirkin2015-07-231-0/+12
* nvc0/ir: cleanup private enums that have graduated to galliumIlia Mirkin2015-07-231-5/+0
* nvc0/ir: allow tess eval output loads to be CSE'dIlia Mirkin2015-07-231-0/+2
* nvc0/ir: add hazard for 2nd dim of vfetch/load indirect argumentIlia Mirkin2015-07-231-0/+2
* nvc0/ir: patch vertex count is stored in the upper bitsIlia Mirkin2015-07-231-0/+4
* nvc0/ir: add support for reading outputs in tess control shadersIlia Mirkin2015-07-232-2/+18
* nvc0/ir: set perPatch flag on load/stores to per-patch varyingsIlia Mirkin2015-07-231-2/+6
* nvc0/ir: populate info structure based on new tess propertiesIlia Mirkin2015-07-231-0/+18
* nvc0/ir: mark varyings as per-patch based on semantic nameIlia Mirkin2015-07-231-0/+14
* nvc0: TESSCOORD comes in as a sysval, not an inputIlia Mirkin2015-07-231-2/+0
* nvc0: preliminary tess supportIlia Mirkin2015-07-233-7/+4
* nouveau: use bool instead of booleanSamuel Pitoiset2015-07-213-12/+12
* gm107/ir: fix indirect txq emissionIlia Mirkin2015-07-181-2/+8
* nvc0/ir: don't worry about sampler in txq handlingIlia Mirkin2015-07-181-22/+8
* nvc0/ir: fix txq on indirect samplersIlia Mirkin2015-07-182-2/+56
* nv50/ir: UCMP arguments are float, so make sure modifiers are appliedIlia Mirkin2015-07-031-1/+2
* nv50/ir: don't emit src2 in immediate formIlia Mirkin2015-07-021-2/+2
* nv50/ir: copy joinAt when splitting both before and afterIlia Mirkin2015-07-013-0/+5
* nv50/ir: fix emission of address reg in 3rd sourceIlia Mirkin2015-06-301-2/+6
* nv50/ir: propagate modifier to right arg when const-folding madIlia Mirkin2015-06-261-1/+4
* nvc0/ir: can't have a join on a load with an indirect sourceIlia Mirkin2015-06-171-1/+1
* nvc0/ir: fix collection of first uses for texture barrier insertionIlia Mirkin2015-06-151-5/+11
* nv50/ir: OP_JOIN is a flow instructionJürgen Rühle2015-06-151-1/+1
* nv50/ir: avoid messing up arg1 of PFETCHIlia Mirkin2015-05-231-2/+18
* nvc0/ir: LOAD's can't be used for shader inputsIlia Mirkin2015-05-222-0/+2
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